Page Frame 4 1 TLB TAG DATA TAG DATA Set 0 00 Set 1 00 01 10 н Cache Frame Valid 3 Page table Block Frame 2 3 2 T.... Н .... 3. 1. 012 34 567 Main memory Page Block 4 8 10 5 11 12 6. 13 14 15 Virtual memory for process P ABCDEEGHISYLMNOP 1. 2. 4.
You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set-associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame.
Given the system state as depicted above, Show the address format for virtual address 0x12 (specify field name and size) that would be used by the system to translate to a physical address and then translate this virtual address into the corresponding physical address. (Hint: Convert the address to its binary equivalent and divide it into the appropriate fields.) Explain how these fields are used to translate to the corresponding physical address.
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