What are the contents of the ROM location in address = 01100mo1o is: o 0000100000011om O 10100000000000m o 00001000010110100 O 00000010100000100 O 00000001100000000
What are the contents of the ROM location in address = 01100mo1o is: o 0000100000011om O 10100000000000m o 00001000010110100 O 00000010100000100 O 00000001100000000
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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![Assume that the main control unit of the Multi-Cycle CPU is implemented as a single ROM of
size 2 x 17 bits as taught in the class
The 12-bit address lines are ordered os (Opl6.0). Zero Flog s[30]} withe
• Opl6) as the most signiticant address bit and
• slo] as the least significant address bit.
Also, assume that the content of each ROM location is similar to the figure below (which is not
the some as the one given to you in the class) with
ALUOP(1) as the most significont bit and
NS(0) as the least significant bit.
Answer the following question:
10
Current State (S,S,S,S)
Input (Opcode + Zero Flag!
Next State (NS,NS,NS,NS)
0000 (Statel)
000
Ople0 - 0000011 (LD)
Ople.0) = 0100011 (SD)
0001 (Statel)
0010
0001 (Statel)
0010
0001 (Statel)
Ople:0) - 0110011 (R-format)
O110
Ople:0- 1100011 (BEQ)
Opls0 = 0000011 (LD)
0001 (Statel)
1000
0010 (State2)
0011
0010 (State)
Ople0 = 010001 (SD)
0101
0011 (State3)
0100
0100 (Stated)
0000
0101 (States)
0000
0110 (Statet)
0111 (State7)
0000
(Opl60)- XXXXNN) dele (Zero Flag - 1)
(Opj60] = xxxxx) dele (Zero Flag 0)
1000 (States)
0000
1000 (States)
1001
1001 (State)
Ople0 = xXxx
0000
Current
State
(S,S,S,S)
0000 (State0)
1
0001 (Statel)
X
1
0010 (State2)
X
X
0011 (State3)
1
0100 (Statet)
1
1
1
1
0101 (State5)
1
1
1
0110 (State6)
1
1
0111 (State7)
1
1
1
1000 (State8)
1
1
X
0.
1
1
1001 (State9)
1
1
What gre the contents of the ROM location in address = 01100mmono is:
O 0000100000onom
০
O 10100000000000111
00001000010110100
O 00000010100000100
O 00000001100000000
PCWrite
Branch
MemRead
MemWrite
IRWrite
MemToReg
* ALUOP<1>
<0>don1V
* ALUSrcB<1>
ALUSrcB<0>
ALUSrcA
RegWrite](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F2f195993-1981-40b2-a909-c19b097ead23%2F2f1d89f7-8238-458d-84ce-feda5cebc1cc%2F37n49o4_processed.jpeg&w=3840&q=75)
Transcribed Image Text:Assume that the main control unit of the Multi-Cycle CPU is implemented as a single ROM of
size 2 x 17 bits as taught in the class
The 12-bit address lines are ordered os (Opl6.0). Zero Flog s[30]} withe
• Opl6) as the most signiticant address bit and
• slo] as the least significant address bit.
Also, assume that the content of each ROM location is similar to the figure below (which is not
the some as the one given to you in the class) with
ALUOP(1) as the most significont bit and
NS(0) as the least significant bit.
Answer the following question:
10
Current State (S,S,S,S)
Input (Opcode + Zero Flag!
Next State (NS,NS,NS,NS)
0000 (Statel)
000
Ople0 - 0000011 (LD)
Ople.0) = 0100011 (SD)
0001 (Statel)
0010
0001 (Statel)
0010
0001 (Statel)
Ople:0) - 0110011 (R-format)
O110
Ople:0- 1100011 (BEQ)
Opls0 = 0000011 (LD)
0001 (Statel)
1000
0010 (State2)
0011
0010 (State)
Ople0 = 010001 (SD)
0101
0011 (State3)
0100
0100 (Stated)
0000
0101 (States)
0000
0110 (Statet)
0111 (State7)
0000
(Opl60)- XXXXNN) dele (Zero Flag - 1)
(Opj60] = xxxxx) dele (Zero Flag 0)
1000 (States)
0000
1000 (States)
1001
1001 (State)
Ople0 = xXxx
0000
Current
State
(S,S,S,S)
0000 (State0)
1
0001 (Statel)
X
1
0010 (State2)
X
X
0011 (State3)
1
0100 (Statet)
1
1
1
1
0101 (State5)
1
1
1
0110 (State6)
1
1
0111 (State7)
1
1
1
1000 (State8)
1
1
X
0.
1
1
1001 (State9)
1
1
What gre the contents of the ROM location in address = 01100mmono is:
O 0000100000onom
০
O 10100000000000111
00001000010110100
O 00000010100000100
O 00000001100000000
PCWrite
Branch
MemRead
MemWrite
IRWrite
MemToReg
* ALUOP<1>
<0>don1V
* ALUSrcB<1>
ALUSrcB<0>
ALUSrcA
RegWrite
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