Question Number: 16TimaA computer system with paging-based memorymanagement, whose architecture allows for a 4GBvirtual address space for processes. The size oflogical pages and physical frames is 4KB. The systemhas 8GB of physical RAM. Assume that each pagetable entry requires an additional 10 bits (beyond theframe number) to store various flags. Assume pagetable entries are rounded up to the nearest byte.Consider the memory required for both outer andinner page tables.Assuming the OS uses hierarchical paging, calculatethe maximum memory space required to store thepage table of a process in the system?

According to the information provided in the initial question, we must determine the amount of space…

Answered: A computer system with paging-based…

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. How many bits are used for the page number? How many bits are used for the offset? 8 bits each. With this system, what’s the maximum number of pages that a process can have? 256 Suppose that each entry in the page table comprises 4 bytes (including the frame number, the valid bit, and miscellaneous “bookkeeping bits”). An OS uses an array to store the page table. What is the size of the page table? 1024 Bytes Furthermore, suppose the first 6 pages of a process map to frames 222 to 227 (as decimal numbers), and the last 5 pages of the process map to frames 1 to 5 (also decimal numbers). All other pages are invalid. Draw the page table, including the valid bit and the frame number. DONE Translate the following virtual addresses to physical addresses, and show how you obtain the answers. (Hint: You do not need to convert…
Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain in bytes/s? To increase its performance, would it be better to make its external data bus 32 bits or to double the external clock fre- quency supplied to the microprocessor? State any other assumptions you make and explain. Hint: Determine the number of bytes that can be transferred per bus cycle.
Consider an operating system using memory mapping on a page basis and using a single level page table. Assume that the necessary page table is always in memory. The system takes 200 ns to make a memory reference, how long does a paged memory reference take? Group of answer choices 400 ns (nanoseconds) 809.2 ms (microseconds) 200 ns (nanoseconds) 1638.4 ms (microseconds)
Consider a CPU that operates with a data transfer rate of 30 Mbytes/s. The data is transferred byte-wise and the CPU has to transfer 30bytes of data, and the size of the Status register is 4 bytes. What is the total time needed to perform the data transfer?
Consider a CPU which operates with 20Mbyte/s operating speed. The CPU is operating on program control mode of I/O and it has to transfer data of 20 bytes from it. The data is transferred byte wise. Size of the Status register is 2 bytes. What is the total time needed to perform the data transfer?
Given a virtual memory of size 4 GiB, physical memory of size 512 KiB, and page size equal to 4 KiB. How many bits are used to specify a physical page number?
Given a virtual memory of size 4 GiB, physical memory of size 1 GiB, and page size equal to 256 KiB. How many bits are used to specify a virtual page number?
We consider a virtual memory design for a computer architecture. Suppose that the byte- addressed computer has 256 bytes pages, 16-bit virtual addresses, and 16-bit page table entries (PTE) (NUM 1 bits of one PTE are used for reference, valid checking, protection mechanism, etc.). The computer uses two-level hierarchical page tables. 1. How many virtual pages can be addressed by the architecture? 2. What is the maximal size of the physical memory that can be supported by the architec- ture? 3. We are now running a program which is using 300 bytes of memory currently. What is the smallest possible number of PTES to store the running program?
3
1. Consider a computer system with a 30-bit logical address and 4-KB page size. The systemsupports up to 512 MB of physical memory. How many entries are there in each of the following?Assume that each page table entry is 4 Bytes.c. A conventional single-level page table?d. An inverted page table?e. A two-level hierarchical page table? 2. Consider a virtual memory system with a 50-bit logical address and a 38-bit physical address.Suppose that the page/frame size is 16K bytes. Assume that each page table entry is 4 Bytes.a. How many frames are in the systems? How many pages in the virtual address space for aprocess?b. If a single-level page table is deployed, calculate the size of the page table for each process.c. Design a multilevel page table structure for this system to ensure that each page table can fitinto one frame. How many levels do you need? Draw a figure to show your page systems
Suppose a computer system uses 16 but addresses for both virtual and physical address. In addition, assume each page (and frame) has a size of 256 bytes. -How many bits are used for page number? -How many bits for offset? -what is the max number of pages a process can have?
Consider a paged virtual memory system in which a process is allocated with 4 frames. The contents of the page map table are given below with two frames being empty. PageActual frame address in memory 4 122 344 477 898 Assume that the order in which the pages appear is the order in which the pages were added to the table (i.e., Page 2 was accessed after Page 4) Assume that the subsequent page accessing is : 1,2,3,4,1,2,5 Using LRU page-replacement algorithm, What frame is accessed by Page 5. 477 O 344 122 O 898

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