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Memory Interfacing: Q2. (a) For a 64 Kbit symmetric memory IC, determine the number of transistors needed to implement a tree type column decoder circuit. If a bit-line type column decoder is now used instead, how many transistors will be correspondingly required? (b) (i) In a 4 Mbit symmetric dynamic RAM (DRAM) IC, each memory cell has a gate capacitance of 0.95 fF and parasitic capacitance of 0.05 fF. If the polysilicon resistance of each cell is 100 2, calculate the delay from the row line operation. Neglect any delay associated with the row decoder circuit. Specify units at every stage of your computation. (ii) It is desirable that the row line delay be not more than 45 nsec. What could be the largest capacity, in number of bits stored, of the memory IC can be? Assume no row line partition has been carried out. Specify units at every stage of your computation.

Memory Interfacing: Q2. (a) For a 64 Kbit symmetric memory IC, determine the number of transistors needed to implement a tree type column decoder circuit. If a bit-line type column decoder is now used instead, how many transistors will be correspondingly required? (b) (i) In a 4 Mbit symmetric dynamic RAM (DRAM) IC, each memory cell has a gate capacitance of 0.95 fF and parasitic capacitance of 0.05 fF. If the polysilicon resistance of each cell is 100 2, calculate the delay from the row line operation. Neglect any delay associated with the row decoder circuit. Specify units at every stage of your computation. (ii) It is desirable that the row line delay be not more than 45 nsec. What could be the largest capacity, in number of bits stored, of the memory IC can be? Assume no row line partition has been carried out. Specify units at every stage of your computation.

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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Memory Interfacing: Q2. (a) For a 64 Kbit symmetric memory IC, determine the number of transistors needed to implement a tree type column decoder circuit. If a bit-line type column decoder is now used instead, how many transistors will be correspondingly required? (b) (i) In a 4 Mbit symmetric dynamic RAM (DRAM) IC, each memory cell has a gate capacitance of 0.95 fF and parasitic capacitance of 0.05 fF. If the polysilicon resistance of each cell is 100 2, calculate the delay from the row line operation. Neglect any delay associated with the row decoder circuit. Specify units at every stage of your computation. (ii) It is desirable that the row line delay be not more than 45 nsec. What could be the largest capacity, in number of bits stored, of the memory IC can be? Assume no row line partition has been carried out. Specify units at every stage of your computation.
Transcribed Image Text:Memory Interfacing: Q2. (a) For a 64 Kbit symmetric memory IC, determine the number of transistors needed to implement a tree type column decoder circuit. If a bit-line type column decoder is now used instead, how many transistors will be correspondingly required? (b) (i) In a 4 Mbit symmetric dynamic RAM (DRAM) IC, each memory cell has a gate capacitance of 0.95 fF and parasitic capacitance of 0.05 fF. If the polysilicon resistance of each cell is 100 2, calculate the delay from the row line operation. Neglect any delay associated with the row decoder circuit. Specify units at every stage of your computation. (ii) It is desirable that the row line delay be not more than 45 nsec. What could be the largest capacity, in number of bits stored, of the memory IC can be? Assume no row line partition has been carried out. Specify units at every stage of your computation.
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