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a) Which model do you generally apply when solving for nodal voltages in a MOSFET circuit? Unified model Switch model Propagation delay RC model Choices: b) Which model do you apply when finding the propagation delay through a logic gate? Choices: Switch model and Elmore delay Unified model c) How do you typically size separate logic gates in your CMOS circuit? Choices: Match unit-sized inverter Maximize area because it will be much faster! d) Circle all disadvantages you might see in ratioed logic: Choices: Takes up more area Noise-margins increased Static power increased

a) Which model do you generally apply when solving for nodal voltages in a MOSFET circuit? Unified model Switch model Propagation delay RC model Choices: b) Which model do you apply when finding the propagation delay through a logic gate? Choices: Switch model and Elmore delay Unified model c) How do you typically size separate logic gates in your CMOS circuit? Choices: Match unit-sized inverter Maximize area because it will be much faster! d) Circle all disadvantages you might see in ratioed logic: Choices: Takes up more area Noise-margins increased Static power increased

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
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a) Which model do you generally apply when solving for nodal voltages in a MOSFET circuit? Unified model Switch model Propagation delay RC model Choices: b) Which model do you apply when finding the propagation delay through a logic gate? Choices: Switch model and Elmore delay Unified model c) How do you typically size separate logic gates in your CMOS circuit? Choices: Match unit-sized inverter Maximize area because it will be much faster! d) Circle all disadvantages you might see in ratioed logic: Choices: Takes up more area Noise-margins increased Static power increased
Transcribed Image Text:a) Which model do you generally apply when solving for nodal voltages in a MOSFET circuit? Unified model Switch model Propagation delay RC model Choices: b) Which model do you apply when finding the propagation delay through a logic gate? Choices: Switch model and Elmore delay Unified model c) How do you typically size separate logic gates in your CMOS circuit? Choices: Match unit-sized inverter Maximize area because it will be much faster! d) Circle all disadvantages you might see in ratioed logic: Choices: Takes up more area Noise-margins increased Static power increased
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