lw r1,12(r7) lw r2,16(r7) add r1,r1,r2 sw r1,4(r5) a. Identify and describe all the data dependencies. b. How many clock cycles does it take to execute this code without any pipelining? c. How many clock cycles with pipelining, but no bypassing (stalls cause the pipeline to wait until previous instruction is finished)?

Computer Networking: A Top-Down Approach (7th Edition)
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Author:James Kurose, Keith Ross
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lw r1,12(r7)
lw r2,16(r7)
add r1,r1,r2
sw r1,4(r5)
a. Identify and describe all the data dependencies.
b. How many clock cycles does it take to execute this code without any pipelining?
c. How many clock cycles with pipelining, but no bypassing (stalls cause the pipeline to wait until previous instruction is finished)?

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