K Q2/ Consider the system G(S) H(S)=1.5 0.4923. S(S+1)(S+2) a. Evaluate the steady-state error for a unit ramp input. b. Design a lag compensator to improve the steady-state error by a factor of 10(increase the static velocity error constant Kv to about 10 times) to get a new dominant closed-loop poles. s=-0.3± j0.55. place the zero of the lag compensator at s=-0.05 c. if R1= 10K, R2=5K2, R3= 10K2 design the lag compensator using Op amp
K Q2/ Consider the system G(S) H(S)=1.5 0.4923. S(S+1)(S+2) a. Evaluate the steady-state error for a unit ramp input. b. Design a lag compensator to improve the steady-state error by a factor of 10(increase the static velocity error constant Kv to about 10 times) to get a new dominant closed-loop poles. s=-0.3± j0.55. place the zero of the lag compensator at s=-0.05 c. if R1= 10K, R2=5K2, R3= 10K2 design the lag compensator using Op amp
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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Transcribed Image Text:K
Q2/ Consider the system G(S)
H(S)=1.5 0.4923.
S(S+1)(S+2)
a. Evaluate the steady-state error for a unit ramp input.
b. Design a lag compensator to improve the steady-state error by a factor of
10(increase the static velocity error constant Kv to about 10 times) to get a new
dominant closed-loop poles. s=-0.3± j0.55. place the zero of the lag compensator
at s=-0.05
c. if R1= 10K, R2=5K2, R3= 10K2 design the lag compensator using Op amp
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