In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. To solve the problems in this exercise, you may find it helpful to draw a table like the one below, as demonstrated for the address sequence “0, 1, 2, 3, 4.” Consider the following address sequence: 0, 2, 4, 8, 10, 12, 14, 8, 0. 5.1 – Assuming an LRU replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed. 5.2 – Assuming an MRU (most recently used) replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed.
In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. To solve the problems in this exercise, you may find it helpful to draw a table like the one below, as demonstrated for the address sequence “0, 1, 2, 3, 4.”
Consider the following address sequence: 0, 2, 4, 8, 10, 12, 14, 8, 0.
5.1 – Assuming an LRU replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed.
5.2 – Assuming an MRU (most recently used) replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed.
![Address of
Contents of Cache Blocks After Reference
Memory
Evicted
Block Accessed Hit or Miss
Block
Set 0
Set 0
Set 1
Set 1
Miss
Mem[0]
1
Miss
Mem[0]
Mem[1]
2
Miss
Mem[0]
Mem[2]
Mem[1]
Miss
Mem[0]
Mem[2]
Mem[1]
Mem[3]
4
Miss
Mem[4]
Mem[2]
Mem[1]
Mem[3]](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fc9265438-da8a-4e52-b5fb-8004adc3507d%2F1badff8b-36e4-4fa1-b0f7-cfc83d88a44d%2Fh27yvr_processed.jpeg&w=3840&q=75)
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