In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. To solve the problems in this exercise, you may find it helpful to draw a table like the one below, as demonstrated for the address sequence “0, 1, 2, 3, 4.”   Consider the following address sequence: 0, 2, 4, 8, 10, 12, 14, 8, 0. 5.1 – Assuming an LRU replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed. 5.2 – Assuming an MRU (most recently used) replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed.

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
icon
Related questions
Question

In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. To solve the problems in this exercise, you may find it helpful to draw a table like the one below, as demonstrated for the address sequence “0, 1, 2, 3, 4.”

 

Consider the following address sequence: 0, 2, 4, 8, 10, 12, 14, 8, 0.


5.1 – Assuming an LRU replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed.


5.2 – Assuming an MRU (most recently used) replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed.

Address of
Contents of Cache Blocks After Reference
Memory
Evicted
Block Accessed Hit or Miss
Block
Set 0
Set 0
Set 1
Set 1
Miss
Mem[0]
1
Miss
Mem[0]
Mem[1]
2
Miss
Mem[0]
Mem[2]
Mem[1]
Miss
Mem[0]
Mem[2]
Mem[1]
Mem[3]
4
Miss
Mem[4]
Mem[2]
Mem[1]
Mem[3]
Transcribed Image Text:Address of Contents of Cache Blocks After Reference Memory Evicted Block Accessed Hit or Miss Block Set 0 Set 0 Set 1 Set 1 Miss Mem[0] 1 Miss Mem[0] Mem[1] 2 Miss Mem[0] Mem[2] Mem[1] Miss Mem[0] Mem[2] Mem[1] Mem[3] 4 Miss Mem[4] Mem[2] Mem[1] Mem[3]
Expert Solution
trending now

Trending now

This is a popular solution!

steps

Step by step

Solved in 2 steps with 2 images

Blurred answer
Similar questions
Recommended textbooks for you
Database System Concepts
Database System Concepts
Computer Science
ISBN:
9780078022159
Author:
Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:
McGraw-Hill Education
Starting Out with Python (4th Edition)
Starting Out with Python (4th Edition)
Computer Science
ISBN:
9780134444321
Author:
Tony Gaddis
Publisher:
PEARSON
Digital Fundamentals (11th Edition)
Digital Fundamentals (11th Edition)
Computer Science
ISBN:
9780132737968
Author:
Thomas L. Floyd
Publisher:
PEARSON
C How to Program (8th Edition)
C How to Program (8th Edition)
Computer Science
ISBN:
9780133976892
Author:
Paul J. Deitel, Harvey Deitel
Publisher:
PEARSON
Database Systems: Design, Implementation, & Manag…
Database Systems: Design, Implementation, & Manag…
Computer Science
ISBN:
9781337627900
Author:
Carlos Coronel, Steven Morris
Publisher:
Cengage Learning
Programmable Logic Controllers
Programmable Logic Controllers
Computer Science
ISBN:
9780073373843
Author:
Frank D. Petruzella
Publisher:
McGraw-Hill Education