A 3-processor systems implements cache coherence with a snoopy MESI protocol. For each access in the sequence below (to the same BLOCK address), list the coherence states (M/E/S/I) for each processor's cache after the access. Assume all the cache states begin in the Invalid (1) state. Event P1 state P2 state P3 state P1 reads P2 writes P2 reads P3 writes
A 3-processor systems implements cache coherence with a snoopy MESI protocol. For each access in the sequence below (to the same BLOCK address), list the coherence states (M/E/S/I) for each processor's cache after the access. Assume all the cache states begin in the Invalid (1) state. Event P1 state P2 state P3 state P1 reads P2 writes P2 reads P3 writes
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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