In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this question assume that individual stages of the datapath have the following latencies:   IF Id EX MEM WB a 250ps 350ps 150ps 300ps 200ps b 200ps 170ps 220ps 210ps 150ps Questions: 3.1.         What is the clock cycle time in a pipelined and non-pipelined processor? What is the total latency of an LDUR instruction in a pipelined and non-pipelined processor? 3.3          If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?

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Q: Refer to the screenshot;

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A: Step 1: Step 2: Step 3: Step 4: