) We examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 200 ps 300 ps 150 ps 250 ps 200 ps Also, assume that instructions executed by the processor are broken down as follows: alu (i.e. add, sub,…) beq lw sw 45 % 20 % 20 % 15% a.) What is the clock cycle time in a pipelined and non-pipelined processor? b.) What is the total latency of seven LW instructions in a pipelined and non-pipelined processor (assume no stalls or hazards) c.) Assuming there are no stalls or hazards, what is the utilization of the data memory? (Hint) R-type instruction: IF ID EX MEM WB: no data memory access required beq: no data memory access required lw: IF ID EX MEM WB: data memory access required sw: IF ID EX MEM WB: data memory access required % of lw + % of sw = ?
) We examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 200 ps 300 ps 150 ps 250 ps 200 ps Also, assume that instructions executed by the processor are broken down as follows: alu (i.e. add, sub,…) beq lw sw 45 % 20 % 20 % 15% a.) What is the clock cycle time in a pipelined and non-pipelined processor? b.) What is the total latency of seven LW instructions in a pipelined and non-pipelined processor (assume no stalls or hazards) c.) Assuming there are no stalls or hazards, what is the utilization of the data memory? (Hint) R-type instruction: IF ID EX MEM WB: no data memory access required beq: no data memory access required lw: IF ID EX MEM WB: data memory access required sw: IF ID EX MEM WB: data memory access required % of lw + % of sw = ?
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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- ) We examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies:
|
IF |
ID |
EX |
MEM |
WB |
|
200 ps |
300 ps |
150 ps |
250 ps |
200 ps |
Also, assume that instructions executed by the processor are broken down as follows:
|
alu (i.e. add, sub,…) |
beq |
lw |
sw |
|
45 % |
20 % |
20 % |
15% |
a.) What is the clock cycle time in a pipelined and non-pipelined processor?
b.) What is the total latency of seven LW instructions in a pipelined and non-pipelined processor (assume no stalls or hazards)
c.) Assuming there are no stalls or hazards, what is the utilization of the data memory?
(Hint)
R-type instruction: IF ID EX MEM WB: no data memory access required
beq: no data memory access required
lw: IF ID EX MEM WB: data memory access required
sw: IF ID EX MEM WB: data memory access required
% of lw + % of sw = ?
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