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2) Consider the complete datapath as shown in Figure 4.15 below. Additionally, assume that the following latencies would be associated with the datapath: Operation Latency (time) Fetch instruction - Mem(PC) 2 ns Read from register file 2 ns ALU operation 3 ns Increment PC by 4 1 ns Change PC depending on 1 ns conditional branch instruction Access data memory 2 ns Register write back 2 ns a) Which MIPS instruction will set the clock cycle time (and hence the clock rate)? b) Given the latencies from the table, what would be the clock rate for this single cycle datapath? Show all work. Add Shift RegWrite left 2, ALU Addresult Instruction [25:21] PC Read address Instruction [20:16] Instruction [31:0] Instruction memory Instruction [15:11] Read register 1 Read register 2 Write register Read data 1 ALUSrc Zero Read data 2 OMX ALU ALU result Write data Registers RegDst Instruction [15:0] 16 32 Sign- extend ALU control Instruction [5:0] ALUOP PCSrc MemWrite MemtoReg Read Address data Data Write memory data MemRead -MOXO) FIGURE 4.15 The datapath of Figure 4.11 with all necessary multiplexors and all control lines identified. The control lines are shown in color. The ALU control block has also been added. The PC does not require a write control, since it is written once at the end of every clock cycle; the branch control logic determines whether it is written with the incremented PC or the branch target address.

2) Consider the complete datapath as shown in Figure 4.15 below. Additionally, assume that the following latencies would be associated with the datapath: Operation Latency (time) Fetch instruction - Mem(PC) 2 ns Read from register file 2 ns ALU operation 3 ns Increment PC by 4 1 ns Change PC depending on 1 ns conditional branch instruction Access data memory 2 ns Register write back 2 ns a) Which MIPS instruction will set the clock cycle time (and hence the clock rate)? b) Given the latencies from the table, what would be the clock rate for this single cycle datapath? Show all work. Add Shift RegWrite left 2, ALU Addresult Instruction [25:21] PC Read address Instruction [20:16] Instruction [31:0] Instruction memory Instruction [15:11] Read register 1 Read register 2 Write register Read data 1 ALUSrc Zero Read data 2 OMX ALU ALU result Write data Registers RegDst Instruction [15:0] 16 32 Sign- extend ALU control Instruction [5:0] ALUOP PCSrc MemWrite MemtoReg Read Address data Data Write memory data MemRead -MOXO) FIGURE 4.15 The datapath of Figure 4.11 with all necessary multiplexors and all control lines identified. The control lines are shown in color. The ALU control block has also been added. The PC does not require a write control, since it is written once at the end of every clock cycle; the branch control logic determines whether it is written with the incremented PC or the branch target address.

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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2) Consider the complete datapath as shown in Figure 4.15 below. Additionally, assume that the following latencies would be associated with the datapath: Operation Latency (time) Fetch instruction - Mem(PC) 2 ns Read from register file 2 ns ALU operation 3 ns Increment PC by 4 1 ns Change PC depending on 1 ns conditional branch instruction Access data memory 2 ns Register write back 2 ns a) Which MIPS instruction will set the clock cycle time (and hence the clock rate)? b) Given the latencies from the table, what would be the clock rate for this single cycle datapath? Show all work. Add Shift RegWrite left 2, ALU Addresult Instruction [25:21] PC Read address Instruction [20:16] Instruction [31:0] Instruction memory Instruction [15:11] Read register 1 Read register 2 Write register Read data 1 ALUSrc Zero Read data 2 OMX ALU ALU result Write data Registers RegDst Instruction [15:0] 16 32 Sign- extend ALU control Instruction [5:0] ALUOP PCSrc MemWrite MemtoReg Read Address data Data Write memory data MemRead -MOXO) FIGURE 4.15 The datapath of Figure 4.11 with all necessary multiplexors and all control lines identified. The control lines are shown in color. The ALU control block has also been added. The PC does not require a write control, since it is written once at the end of every clock cycle; the branch control logic determines whether it is written with the incremented PC or the branch target address.
Transcribed Image Text:2) Consider the complete datapath as shown in Figure 4.15 below. Additionally, assume that the following latencies would be associated with the datapath: Operation Latency (time) Fetch instruction - Mem(PC) 2 ns Read from register file 2 ns ALU operation 3 ns Increment PC by 4 1 ns Change PC depending on 1 ns conditional branch instruction Access data memory 2 ns Register write back 2 ns a) Which MIPS instruction will set the clock cycle time (and hence the clock rate)? b) Given the latencies from the table, what would be the clock rate for this single cycle datapath? Show all work. Add Shift RegWrite left 2, ALU Addresult Instruction [25:21] PC Read address Instruction [20:16] Instruction [31:0] Instruction memory Instruction [15:11] Read register 1 Read register 2 Write register Read data 1 ALUSrc Zero Read data 2 OMX ALU ALU result Write data Registers RegDst Instruction [15:0] 16 32 Sign- extend ALU control Instruction [5:0] ALUOP PCSrc MemWrite MemtoReg Read Address data Data Write memory data MemRead -MOXO) FIGURE 4.15 The datapath of Figure 4.11 with all necessary multiplexors and all control lines identified. The control lines are shown in color. The ALU control block has also been added. The PC does not require a write control, since it is written once at the end of every clock cycle; the branch control logic determines whether it is written with the incremented PC or the branch target address.
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