2) Consider the complete datapath as shown in Figure 4.15 below. Additionally, assume that the following latencies would be associated with the datapath: Operation Latency (time) Fetch instruction - Mem(PC) 2 ns Read from register file 2 ns ALU operation 3 ns Increment PC by 4 1 ns Change PC depending on 1 ns conditional branch instruction Access data memory 2 ns Register write back 2 ns a) Which MIPS instruction will set the clock cycle time (and hence the clock rate)? b) Given the latencies from the table, what would be the clock rate for this single cycle datapath? Show all work. Add Shift RegWrite left 2, ALU Addresult Instruction [25:21] PC Read address Instruction [20:16] Instruction [31:0] Instruction memory Instruction [15:11] Read register 1 Read register 2 Write register Read data 1 ALUSrc Zero Read data 2 OMX ALU ALU result Write data Registers RegDst Instruction [15:0] 16 32 Sign- extend ALU control Instruction [5:0] ALUOP PCSrc MemWrite MemtoReg Read Address data Data Write memory data MemRead -MOXO) FIGURE 4.15 The datapath of Figure 4.11 with all necessary multiplexors and all control lines identified. The control lines are shown in color. The ALU control block has also been added. The PC does not require a write control, since it is written once at the end of every clock cycle; the branch control logic determines whether it is written with the incremented PC or the branch target address.
2) Consider the complete datapath as shown in Figure 4.15 below. Additionally, assume that the following latencies would be associated with the datapath: Operation Latency (time) Fetch instruction - Mem(PC) 2 ns Read from register file 2 ns ALU operation 3 ns Increment PC by 4 1 ns Change PC depending on 1 ns conditional branch instruction Access data memory 2 ns Register write back 2 ns a) Which MIPS instruction will set the clock cycle time (and hence the clock rate)? b) Given the latencies from the table, what would be the clock rate for this single cycle datapath? Show all work. Add Shift RegWrite left 2, ALU Addresult Instruction [25:21] PC Read address Instruction [20:16] Instruction [31:0] Instruction memory Instruction [15:11] Read register 1 Read register 2 Write register Read data 1 ALUSrc Zero Read data 2 OMX ALU ALU result Write data Registers RegDst Instruction [15:0] 16 32 Sign- extend ALU control Instruction [5:0] ALUOP PCSrc MemWrite MemtoReg Read Address data Data Write memory data MemRead -MOXO) FIGURE 4.15 The datapath of Figure 4.11 with all necessary multiplexors and all control lines identified. The control lines are shown in color. The ALU control block has also been added. The PC does not require a write control, since it is written once at the end of every clock cycle; the branch control logic determines whether it is written with the incremented PC or the branch target address.
Chapter4: Processor Technology And Architecture
Section: Chapter Questions
Problem 15VE: A(n) ________________ instruction always alters the instruction execution sequence. A(n)...
Related questions
Question
Refer to the screenshot;
![2)
Consider the complete datapath as shown in Figure 4.15 below. Additionally, assume
that the following latencies would be associated with the datapath:
Operation
Latency (time)
Fetch instruction - Mem(PC)
2 ns
Read from register file
2 ns
ALU operation
3 ns
Increment PC by 4
1 ns
Change PC depending on
1 ns
conditional branch instruction
Access data memory
2 ns
Register write back
2 ns
a) Which MIPS instruction will set the clock cycle time (and hence the clock rate)?
b)
Given the latencies from the table, what would be the clock rate for this single
cycle datapath? Show all work.
Add
Shift
RegWrite
left 2,
ALU
Addresult
Instruction [25:21]
PC
Read
address
Instruction [20:16]
Instruction
[31:0]
Instruction
memory
Instruction [15:11]
Read
register 1
Read
register 2
Write
register
Read
data 1
ALUSrc
Zero
Read
data 2
OMX
ALU ALU
result
Write
data Registers
RegDst
Instruction [15:0]
16
32
Sign-
extend
ALU
control
Instruction [5:0]
ALUOP
PCSrc
MemWrite
MemtoReg
Read
Address data
Data
Write memory
data
MemRead
-MOXO)
FIGURE 4.15 The datapath of Figure 4.11 with all necessary multiplexors and all control lines identified. The control
lines are shown in color. The ALU control block has also been added. The PC does not require a write control, since it is written once at the end
of every clock cycle; the branch control logic determines whether it is written with the incremented PC or the branch target address.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F6e098a1b-6d5d-48d5-a6ed-26facdf391a7%2Fb2ed56d6-0ab4-4658-a80b-639a9c26c8ea%2Fgleforb_processed.png&w=3840&q=75)
Transcribed Image Text:2)
Consider the complete datapath as shown in Figure 4.15 below. Additionally, assume
that the following latencies would be associated with the datapath:
Operation
Latency (time)
Fetch instruction - Mem(PC)
2 ns
Read from register file
2 ns
ALU operation
3 ns
Increment PC by 4
1 ns
Change PC depending on
1 ns
conditional branch instruction
Access data memory
2 ns
Register write back
2 ns
a) Which MIPS instruction will set the clock cycle time (and hence the clock rate)?
b)
Given the latencies from the table, what would be the clock rate for this single
cycle datapath? Show all work.
Add
Shift
RegWrite
left 2,
ALU
Addresult
Instruction [25:21]
PC
Read
address
Instruction [20:16]
Instruction
[31:0]
Instruction
memory
Instruction [15:11]
Read
register 1
Read
register 2
Write
register
Read
data 1
ALUSrc
Zero
Read
data 2
OMX
ALU ALU
result
Write
data Registers
RegDst
Instruction [15:0]
16
32
Sign-
extend
ALU
control
Instruction [5:0]
ALUOP
PCSrc
MemWrite
MemtoReg
Read
Address data
Data
Write memory
data
MemRead
-MOXO)
FIGURE 4.15 The datapath of Figure 4.11 with all necessary multiplexors and all control lines identified. The control
lines are shown in color. The ALU control block has also been added. The PC does not require a write control, since it is written once at the end
of every clock cycle; the branch control logic determines whether it is written with the incremented PC or the branch target address.
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