In the following problems, unless otherwise stated, assume Cox = 200 A/V², upCox 100 A/V², λ = 0, and VTH = 0.4 V for NMOS devices and -0.4 V for PMOS devices. 7.16. In the common-source stage of Fig. 7.49, W/L = 30/0.18 and λ = 0. (a) What gate voltage yields a drain current of 0.5 mA? (Verify that M₁ operates in saturation.) (b) With such a drain bias current, calculate the voltage gain of the stage. VDD = 1.8 V T Rp 2kQ Vout مـو = VinM₁ Figure 7.49

In the following problems, unless otherwise stated, assume Cox = 200 A/V², upCox 100 A/V², λ = 0, and VTH = 0.4 V for NMOS devices and -0.4 V for PMOS devices. 7.16. In the common-source stage of Fig. 7.49, W/L = 30/0.18 and λ = 0. (a) What gate voltage yields a drain current of 0.5 mA? (Verify that M₁ operates in saturation.) (b) With such a drain bias current, calculate the voltage gain of the stage. VDD = 1.8 V T Rp 2kQ Vout مـو = VinM₁ Figure 7.49

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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