HELP! You have a virtual memory system with a two-entry TLB, a 2-way set associative cache and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided up into blocks, where each block is represented by a letter. Two blocks equals one frame. a)Virtual address page 3, offset 7 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame and what the physical address in binary? Explain your answers. b)Virtual address page 0, offset 1310 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame? Explain your answers. c)Virtual address page 2, offset 3 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame? Explain your answers.
HELP!
You have a virtual memory system with a two-entry TLB, a 2-way set
associative cache and a page table for a process P. Assume cache blocks of 8 bytes and page size
of 16 bytes. In the system below, main memory is divided up into blocks, where each block is
represented by a letter. Two blocks equals one frame.
a)Virtual address page 3, offset 7 results in a TLB hit or miss? If TLB hit, what’s the main
memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main
memory frame and what the physical address in binary? Explain your answers.
b)Virtual address page 0, offset 1310 results in a TLB hit or miss? If TLB hit, what’s the
main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the
main memory frame? Explain your answers.
c)Virtual address page 2, offset 3 results in a TLB hit or miss? If TLB hit, what’s the main
memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main
memory frame? Explain your answers.


Step by step
Solved in 2 steps









