A) Virtual address page 3, offset 7 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame and what the physical address in binary? Explain your answers. B) Virtual address page 0, offset 1310 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame? Explain your answers. C) Virtual address page 2, offset 3 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame? Explain your answers
A) Virtual address page 3, offset 7 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame and what the physical address in binary? Explain your answers. B) Virtual address page 0, offset 1310 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame? Explain your answers. C) Virtual address page 2, offset 3 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame? Explain your answers
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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You have a virtual memory system with a two-entry TLB, a 2-way set associative cache and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided up into blocks, where each block is represented by a letter. Two blocks equals one frame.
A) Virtual address page 3, offset 7 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame and what the physical address in binary? Explain your answers.
B) Virtual address page 0, offset 1310 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame? Explain your answers.
C) Virtual address page 2, offset 3 results in a TLB hit or miss? If TLB hit, what’s the main memory frame? If TLB miss, would it result in a page fault? If not a page fault, what’s the main memory frame? Explain your answers
![**Translation Lookaside Buffer (TLB)**
```
| | |
|---|---|
| 0 | 3 |
| 4 | 1 |
```
**Cache**
```
| Set 0 | tag | C | tag | I |
|-------|-----|---|------|---|
| Set 1 | tag | D | tag | H |
```
**Page Table**
```
| | |
|-------|-------|
| Frame | Valid |
|-------|-------|
| 0 | 3 1 |
| 1 | 0 1 |
| 2 | - 0 |
| 3 | 2 1 |
| 4 | 1 1 |
| 5 | - 0 |
| 6 | - 0 |
```
**Main Memory**
```
| Frame | Block |
|-------|-------|
| 0 | C |
| 1 | D |
| 2 | I |
| 3 | G |
| 4 | H |
| 5 | A |
| 6 | B |
```
**Virtual Memory For Process P**
```
| Page | Block |
|-------|-------|
| 0 | A |
| 1 | B |
| 2 | C |
| 3 | D |
| 4 | E |
| 5 | F |
| 6 | G |
| 7 | H |
| 8 | I |
| 9 | J |
| 10 | K |
| 11 | L |
| 12 | M |
| 13 | N |
| 14 | O |
| 15 | P |
```
### Explanation of Graphs and Diagrams:
1. **Translation Lookaside Buffer (TLB):**
The TLB is a small, fast cache that stores recent translations of virtual memory to physical memory addresses. It has entries as follows:
- Entry [0, 3]
- Entry [4, 1]
2. **Cache:**
- The cache memory is divided into two sets.
- **Set 0](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F360b1677-65a3-43fd-82ea-2835ab5360ed%2F6e38c469-a3c9-48a9-a929-065965ce0199%2F9o3ie7b_processed.jpeg&w=3840&q=75)
Transcribed Image Text:**Translation Lookaside Buffer (TLB)**
```
| | |
|---|---|
| 0 | 3 |
| 4 | 1 |
```
**Cache**
```
| Set 0 | tag | C | tag | I |
|-------|-----|---|------|---|
| Set 1 | tag | D | tag | H |
```
**Page Table**
```
| | |
|-------|-------|
| Frame | Valid |
|-------|-------|
| 0 | 3 1 |
| 1 | 0 1 |
| 2 | - 0 |
| 3 | 2 1 |
| 4 | 1 1 |
| 5 | - 0 |
| 6 | - 0 |
```
**Main Memory**
```
| Frame | Block |
|-------|-------|
| 0 | C |
| 1 | D |
| 2 | I |
| 3 | G |
| 4 | H |
| 5 | A |
| 6 | B |
```
**Virtual Memory For Process P**
```
| Page | Block |
|-------|-------|
| 0 | A |
| 1 | B |
| 2 | C |
| 3 | D |
| 4 | E |
| 5 | F |
| 6 | G |
| 7 | H |
| 8 | I |
| 9 | J |
| 10 | K |
| 11 | L |
| 12 | M |
| 13 | N |
| 14 | O |
| 15 | P |
```
### Explanation of Graphs and Diagrams:
1. **Translation Lookaside Buffer (TLB):**
The TLB is a small, fast cache that stores recent translations of virtual memory to physical memory addresses. It has entries as follows:
- Entry [0, 3]
- Entry [4, 1]
2. **Cache:**
- The cache memory is divided into two sets.
- **Set 0
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