Consider a CMOS process with VDD = 1.8 V, VTN = 0.7 V, VTP = 0.87 V, kn = 100 μA/V², kp = 30 μA/V². For a pseudo-NMOS inverter sized with (W/L)n = 2 and (W/L)p= 8, find out VOL. Will this device be able to drive another circuit properly? If yes, please justify your answer. If not, please explain a way to solve the issue.

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1. Consider a CMOS process with VDD = 1.8 V, VTN = 0.7 V, VTP = 0.87 V, kn = 100 µA/V², kp = 30
μA/V². For a pseudo-NMOS inverter sized with (W/L)n = 2 and (W/L)p = 8, find out VOL. Will this
device be able to drive another circuit properly? If yes, please justify your answer. If not, please explain
a way to solve the issue.
2.
Design a 3×2-bit multiplier for unsigned numbers. Design it using the Cadence.
3. Sketch a 12-input CMOS OR gate using only NOR gates of no more than 3 inputs each. Compute the
number of NMOS required to design this circuit. Design it using the Cadence.
Transcribed Image Text:1. Consider a CMOS process with VDD = 1.8 V, VTN = 0.7 V, VTP = 0.87 V, kn = 100 µA/V², kp = 30 μA/V². For a pseudo-NMOS inverter sized with (W/L)n = 2 and (W/L)p = 8, find out VOL. Will this device be able to drive another circuit properly? If yes, please justify your answer. If not, please explain a way to solve the issue. 2. Design a 3×2-bit multiplier for unsigned numbers. Design it using the Cadence. 3. Sketch a 12-input CMOS OR gate using only NOR gates of no more than 3 inputs each. Compute the number of NMOS required to design this circuit. Design it using the Cadence.
6. Sketch a 3-input XOR and a 4-to-1 MUX by applying Transmission Gate and Pass-transistor. Compute
the number of transistors required to design those gates. Design and simulate it using the Cadence.
7. Select and analyze a latch that will mitigate all the drawbacks of a transmission gate latch. Distinguish
all the delay elements of a flip-flop.
8.
A 3-input NAND gate is designed using dynamic logic. Compute the output voltage (Vout) for this
circuit when the inputs are 1, 0, 1 (i.e., NMOS2 is receiving 0 input). Design it using the Cadence.
Simulate for different input patterns.
Transcribed Image Text:6. Sketch a 3-input XOR and a 4-to-1 MUX by applying Transmission Gate and Pass-transistor. Compute the number of transistors required to design those gates. Design and simulate it using the Cadence. 7. Select and analyze a latch that will mitigate all the drawbacks of a transmission gate latch. Distinguish all the delay elements of a flip-flop. 8. A 3-input NAND gate is designed using dynamic logic. Compute the output voltage (Vout) for this circuit when the inputs are 1, 0, 1 (i.e., NMOS2 is receiving 0 input). Design it using the Cadence. Simulate for different input patterns.
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