Consider a CMOS inverter, which the following nMOS VTO, n = 0.8 V PMOS VTO, p = -1.0V unCox = 50 μA/V² upCox = 20 μA/V² The power supply voltage is VDD = 5V. Both trans The total output load capacitance of this circ transistors dimensions. i) ii) iii) Determine the channel width of the switching threshold voltage is equal Calculate the average propagration How do the switching threshold Vt supply voltage is dropped from 5 L ros

Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
icon
Related questions
Question
Consider a CMOS inverter, which the following device parameter
nMOS VTO, n = 0.8 V
pMOS VTO, p = -1.0V
unCox = 50 μA/V²
upCox = 20 μA/V²
The power supply voltage is VDD = 5V. Both transistors have a channel length of Ln = Lp = 1 um.
The total output load capacitance of this circuit is Cout= 2 pF, which is independent of
transistors dimensions.
i)
ii)
iii)
Determine the channel width of the nMOS and the pMOS transistors such that the
switching threshold voltage is equal to 2.2 V, and the output rise time is Trise = 5 ns
Calculate the average propagration delay time tp for the circuit designed in (a)
How do the switching threshold Vth and the delay times change if the power
supply voltage is dropped from 5 V to 3.3 V. Provide the interpretation of the
results.
Transcribed Image Text:Consider a CMOS inverter, which the following device parameter nMOS VTO, n = 0.8 V pMOS VTO, p = -1.0V unCox = 50 μA/V² upCox = 20 μA/V² The power supply voltage is VDD = 5V. Both transistors have a channel length of Ln = Lp = 1 um. The total output load capacitance of this circuit is Cout= 2 pF, which is independent of transistors dimensions. i) ii) iii) Determine the channel width of the nMOS and the pMOS transistors such that the switching threshold voltage is equal to 2.2 V, and the output rise time is Trise = 5 ns Calculate the average propagration delay time tp for the circuit designed in (a) How do the switching threshold Vth and the delay times change if the power supply voltage is dropped from 5 V to 3.3 V. Provide the interpretation of the results.
Expert Solution
steps

Step by step

Solved in 2 steps

Blurred answer
Knowledge Booster
P-channel Metal-Oxide Semiconductor (PMOS), N-channel Metal-Oxide Semiconductor (NMOS), and Complementary Metal-Oxide Semiconductor (CMOS)
Learn more about
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, electrical-engineering and related others by exploring similar questions and additional content below.
Similar questions
  • SEE MORE QUESTIONS
Recommended textbooks for you
Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
Electrical Engineering
ISBN:
9780133923605
Author:
Robert L. Boylestad
Publisher:
PEARSON
Delmar's Standard Textbook Of Electricity
Delmar's Standard Textbook Of Electricity
Electrical Engineering
ISBN:
9781337900348
Author:
Stephen L. Herman
Publisher:
Cengage Learning
Programmable Logic Controllers
Programmable Logic Controllers
Electrical Engineering
ISBN:
9780073373843
Author:
Frank D. Petruzella
Publisher:
McGraw-Hill Education
Fundamentals of Electric Circuits
Fundamentals of Electric Circuits
Electrical Engineering
ISBN:
9780078028229
Author:
Charles K Alexander, Matthew Sadiku
Publisher:
McGraw-Hill Education
Electric Circuits. (11th Edition)
Electric Circuits. (11th Edition)
Electrical Engineering
ISBN:
9780134746968
Author:
James W. Nilsson, Susan Riedel
Publisher:
PEARSON
Engineering Electromagnetics
Engineering Electromagnetics
Electrical Engineering
ISBN:
9780078028151
Author:
Hayt, William H. (william Hart), Jr, BUCK, John A.
Publisher:
Mcgraw-hill Education,