A design for a synchronous divide-by-six Gray counter isrequired which meets the following specification.The system has 2 inputs, PAUSE and SKIP:• While PAUSE and SKIP are not asserted (logic 0), thecounter continually loops through the Gray coded binarysequence {0002, 0012, 0112, 0102, 1102, 1112}.• If PAUSE is asserted (logic 1) when the counter is onnumber 0102, it stays here until it becomes unasserted (atwhich point it continues counting as before).• While SKIP is asserted (logic 1), the counter misses outodd numbers, i.e. it loops through the sequence {0002,0112, 1102}.The system has 4 outputs, BIT3, BIT2, BIT1, and WAITING:• BIT3, BIT2, and BIT1 are unconditional outputsrepresenting the current number, where BIT3 is the mostsignificant-bit and BIT1 is the least-significant-bit.• An active-high conditional output WAITING should beasserted (logic 1) whenever the counter is paused at 0102.(a) Draw an ASM chart for a synchronous system to providethe functionality described above.(b) Produce a state transition table from your ASM chart.(c) State whether your design has any unused states (andif so, which ones they are)? Explain how you could usethese for minimisation, and what you would do to ensurethat your system cannot get stuck in an unused state.
A design for a synchronous divide-by-six Gray counter is
required which meets the following specification.
The system has 2 inputs, PAUSE and SKIP:
• While PAUSE and SKIP are not asserted (logic 0), the
counter continually loops through the Gray coded binary
sequence {0002, 0012, 0112, 0102, 1102, 1112}.
• If PAUSE is asserted (logic 1) when the counter is on
number 0102, it stays here until it becomes unasserted (at
which point it continues counting as before).
• While SKIP is asserted (logic 1), the counter misses out
odd numbers, i.e. it loops through the sequence {0002,
0112, 1102}.
The system has 4 outputs, BIT3, BIT2, BIT1, and WAITING:
• BIT3, BIT2, and BIT1 are unconditional outputs
representing the current number, where BIT3 is the mostsignificant-bit and BIT1 is the least-significant-bit.
• An active-high conditional output WAITING should be
asserted (logic 1) whenever the counter is paused at 0102.
(a) Draw an ASM chart for a synchronous system to provide
the functionality described above.
(b) Produce a state transition table from your ASM chart.
(c) State whether your design has any unused states (and
if so, which ones they are)? Explain how you could use
these for minimisation, and what you would do to ensure
that your system cannot get stuck in an unused state.
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