7. Given the MIPS processor in Figure 4, if the control signal "RegWrite" in the processor has a stuck-at-0 fault (meaning that the signal is always 0, regardless of its intended value). Which of the following instructions would fail? And why? MemtoReg Control MemWrite Unit Branch PCSrc ALUControl 3128 Op ALUSrc 5oFunct RegDst RegWrite CLK CLK CLK WE3 A1 Zero PC Instr SrcA WE RD1 PC A RD ALUResult A ReadData RD Instruction Memory 21시 A2 RD2 SrcB Data A3 Register File Memory WriteData WD3 WD 2016 1511 WriteReg PCPlus4 Signimm 150 Sign Extend PCBranch Result Figure 4. Single cycle processor (1) lw Srt, immed($rs) # load word from memory address [$rs]+immed (2) sw (3) add $rd, $rs, $rt (4) addi $rd, $rs, -1 $rt, immed($rs) # store word to memory address [$rs]+immed #[Rd] = [Rs] + [Rt] # [Rd] = [Rs] - 1
7. Given the MIPS processor in Figure 4, if the control signal "RegWrite" in the processor has a stuck-at-0 fault (meaning that the signal is always 0, regardless of its intended value). Which of the following instructions would fail? And why? MemtoReg Control MemWrite Unit Branch PCSrc ALUControl 3128 Op ALUSrc 5oFunct RegDst RegWrite CLK CLK CLK WE3 A1 Zero PC Instr SrcA WE RD1 PC A RD ALUResult A ReadData RD Instruction Memory 21시 A2 RD2 SrcB Data A3 Register File Memory WriteData WD3 WD 2016 1511 WriteReg PCPlus4 Signimm 150 Sign Extend PCBranch Result Figure 4. Single cycle processor (1) lw Srt, immed($rs) # load word from memory address [$rs]+immed (2) sw (3) add $rd, $rs, $rt (4) addi $rd, $rs, -1 $rt, immed($rs) # store word to memory address [$rs]+immed #[Rd] = [Rs] + [Rt] # [Rd] = [Rs] - 1
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
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Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question
![7. Given the MIPS processor in Figure 4, if the control signal "RegWrite" in
the processor has a stuck-at-0 fault (meaning that the signal is always 0,
regardless of its intended value). Which of the following instructions would
fail? And why?
MemtoReg
Control
MemWrite
Unit
Branch
PCSrc
ALUControl,,
31:26
Op
ALUSrc
50
Funct RegDst
RegWrite
CLK
CLK
CLK
Zeo
ALUResult
WE3
RD1
PC
521 A1
SrcA
WE
PC
A
RD LInstr
ReadData
RD
A
Instruction
20 16
A2
SrcB
RD2
Data
Memory
АЗ
Memory
Register
WD3
File
Write Data
WD
20.16
15:11
WriteReg
PCPlus4
Signlmm
<<2
Sign Extend
|РCBranch
Result
Figure 4. Single cycle processor
(1) lw
(2) sw
(3) add $rd, $rs, $rt
(4) addi $rd, $rs, -1
Srt, immed($rs) # load word from memory address [$rs]+immed
$rt, immed($rs) # store word to memory address [$rs]+immed
#[Rd] = [Rs] + [Rt]
# [Rd] = [Rs] - 1
ALU](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fc8742ef3-28b4-4a77-af59-a82416c1307d%2F914a8b2f-2335-41b3-a00a-13ffa29b32ba%2F8uauiw_processed.jpeg&w=3840&q=75)
Transcribed Image Text:7. Given the MIPS processor in Figure 4, if the control signal "RegWrite" in
the processor has a stuck-at-0 fault (meaning that the signal is always 0,
regardless of its intended value). Which of the following instructions would
fail? And why?
MemtoReg
Control
MemWrite
Unit
Branch
PCSrc
ALUControl,,
31:26
Op
ALUSrc
50
Funct RegDst
RegWrite
CLK
CLK
CLK
Zeo
ALUResult
WE3
RD1
PC
521 A1
SrcA
WE
PC
A
RD LInstr
ReadData
RD
A
Instruction
20 16
A2
SrcB
RD2
Data
Memory
АЗ
Memory
Register
WD3
File
Write Data
WD
20.16
15:11
WriteReg
PCPlus4
Signlmm
<<2
Sign Extend
|РCBranch
Result
Figure 4. Single cycle processor
(1) lw
(2) sw
(3) add $rd, $rs, $rt
(4) addi $rd, $rs, -1
Srt, immed($rs) # load word from memory address [$rs]+immed
$rt, immed($rs) # store word to memory address [$rs]+immed
#[Rd] = [Rs] + [Rt]
# [Rd] = [Rs] - 1
ALU
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