Given a machine-code RISC-V instruction is divided as in the figure below, choose the possible assembly instruction which matches the machine-code. Notice that the "?" indicates that the bit could be either "0" or "T. 0000000 00101 00111 ??? 00100 ??????? Name Field Comments (Field size) 7 bits 5 bits 5 bits 3 bits 5 bits 7 bits R-type type Stype SB-type Utype U-type funct7 rs2 rsi funct3 rd opcode Arithmetic instruction format immediate[11:0] rs1 funct3 rd opcode Loads & immediate arithmetic immed[11:5] rs2 rs1 funct3 immed[4:0] opcode Stores immed[12,10:5] rs2 rs1 funct3 immed(4:1,11] opcode Conditional branch format immediate(20,10:1.11.19:12] immediate[31:12] rd opcode Unconditional jump format rd opcode Upper immediate format O blt x5, x7, 2 O sd x7, 2 (x5) bne x7, x5, 4 O bge x5, x7, 2 O sb x5, 4 (x7) O bgeu x7, x5, 4 aja
Given a machine-code RISC-V instruction is divided as in the figure below, choose the possible assembly instruction which matches the machine-code. Notice that the "?" indicates that the bit could be either "0" or "T. 0000000 00101 00111 ??? 00100 ??????? Name Field Comments (Field size) 7 bits 5 bits 5 bits 3 bits 5 bits 7 bits R-type type Stype SB-type Utype U-type funct7 rs2 rsi funct3 rd opcode Arithmetic instruction format immediate[11:0] rs1 funct3 rd opcode Loads & immediate arithmetic immed[11:5] rs2 rs1 funct3 immed[4:0] opcode Stores immed[12,10:5] rs2 rs1 funct3 immed(4:1,11] opcode Conditional branch format immediate(20,10:1.11.19:12] immediate[31:12] rd opcode Unconditional jump format rd opcode Upper immediate format O blt x5, x7, 2 O sd x7, 2 (x5) bne x7, x5, 4 O bge x5, x7, 2 O sb x5, 4 (x7) O bgeu x7, x5, 4 aja
Computer Networking: A Top-Down Approach (7th Edition)
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![Given a machine-code RISC-V instruction is divided as in the figure below, choose the
possible assembly instruction which matches the machine-code.
Notice that the "?" indicates that the bit could be either "0" or T".
0000000
00101 00111 ???
00100 ???????
Name
Field
Comments
(Field size)
7 bits
5 bits
5 bits
3 bits
5 bits
7 bits
Rtype
type
Stype
SB-type
U-type
U-type
funct7
rs2
rs1
funct3
rd
opcode
Arithmetic instruction format
immediate[11:0]
rs1
funct3
rd
opcode
Loads & immediate arithmetic
immed[4:0]
funct3 immed[4:1,11]
immed[11:5]
rs2
rs1
funct3
opcode
Stores
immed[12,10:5]
rs2
rs1
opcode
Conditional branch format
immediate[20,10:1,11,19:12]
immediate(31:12]
rd
opcode
Unconditional jump format
rd
орсоdе
Upper immediate format
O blt x5, x7, 2
O sd x7, 2 (x5)
O bne x7, x5, 4
O bge x5, x7, 2
O sb x5, 4 (x7)
O bgeu x7, x5, 4](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F2efd7fb1-2b55-4b04-b4d4-01e7f06720c4%2F68169946-bd66-4870-9883-c68a931bcbe6%2Fqneohk_processed.jpeg&w=3840&q=75)
Transcribed Image Text:Given a machine-code RISC-V instruction is divided as in the figure below, choose the
possible assembly instruction which matches the machine-code.
Notice that the "?" indicates that the bit could be either "0" or T".
0000000
00101 00111 ???
00100 ???????
Name
Field
Comments
(Field size)
7 bits
5 bits
5 bits
3 bits
5 bits
7 bits
Rtype
type
Stype
SB-type
U-type
U-type
funct7
rs2
rs1
funct3
rd
opcode
Arithmetic instruction format
immediate[11:0]
rs1
funct3
rd
opcode
Loads & immediate arithmetic
immed[4:0]
funct3 immed[4:1,11]
immed[11:5]
rs2
rs1
funct3
opcode
Stores
immed[12,10:5]
rs2
rs1
opcode
Conditional branch format
immediate[20,10:1,11,19:12]
immediate(31:12]
rd
opcode
Unconditional jump format
rd
орсоdе
Upper immediate format
O blt x5, x7, 2
O sd x7, 2 (x5)
O bne x7, x5, 4
O bge x5, x7, 2
O sb x5, 4 (x7)
O bgeu x7, x5, 4
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