Consider the following MIPS instruction: add $t1, $t2, $t3 What is the ALUSrc control signal value: top or bottom? What is the MemtoReg control signal value: top or bottom? What is the PCSrc control signal value: top or bottom?
Consider the following MIPS instruction: add $t1, $t2, $t3 What is the ALUSrc control signal value: top or bottom? What is the MemtoReg control signal value: top or bottom? What is the PCSrc control signal value: top or bottom?
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Consider the following MIPS instruction: add $t1, $t2, $t3
- What is the ALUSrc control signal value: top or bottom?
- What is the MemtoReg control signal value: top or bottom?
- What is the PCSrc control signal value: top or bottom?

Transcribed Image Text:This image illustrates a simplified schematic of a single-cycle CPU datapath, highlighting the flow of data and control signals within the processor. The diagram consists of several key components and pathways connected to facilitate instruction execution.
### Components and Pathways:
1. **PC (Program Counter):**
- Keeps track of the next instruction address. The PC outputs to an adder and to the instruction memory.
2. **Instruction Memory:**
- Receives the address from the PC and outputs the instruction. This instruction is fed to various other components in the system.
3. **Registers:**
- Contains read and write registers and data inputs/outputs. The read register sections output data to the ALU and a multiplexer (Mux).
4. **Adders:**
- There are two adders:
- The first one adds a constant (4) to the PC to get the next sequential instruction address.
- The second adds the ALU result.
5. **ALU (Arithmetic Logic Unit):**
- Responsible for performing operations specified by the ALU operation control signals. It outputs a result and a zero signal indicating if the result is zero.
6. **Sign-extend:**
- Extends the immediate value from 16 bits to 32 bits. This output can be directed to the ALU for arithmetic operations via a Mux.
7. **Shift Left 2:**
- Shifts the sign-extended value left by two bits, typically used for calculating branch target addresses.
8. **Data Memory:**
- Interacts with the ALU result for address input and supports read/write operations with control signals (MemWrite and MemRead).
9. **Multiplexers (Mux):**
- Used to select between different data inputs. Three main multiplexers are shown:
- At the PC source, deciding the next address based on control signals.
- At the ALU source, selecting between register data and sign-extended data.
- At the ALU result, allowing data memory output or ALU result to be written back to registers.
### Control Signals:
- **RegWrite:** Enables writing data to the register.
- **PCSrc:** Controls PC Mux for determining next instruction address.
- **ALUSrc:** Selects input data source for the ALU.
- **MemtoReg:** Selects data to write back to registers from ALU or data memory.
- **MemRead:** Enables
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