3. Design a 4-bit register using D-type Flip Flops that allows operation according to the following table: S1 SO Operation 0 0 Memory (no change) 0 1 Parallel Data Load 1 0 Shift Right 1 1 Ring Counter
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- Design 2 bits counter that count down by using T flip flop when input x =1 and counts upwhen x=0. Find the following1. Derive the state table2. Derive the K‐map simplifications.3. Draw the logic diagramProblem Statement: You design a circuit of a decade counter that will count from 0-9 only. You will only be using the following: (a) Button – only 1 button will be used to trigger the counting. (b) Flip flop IC to used as counting circuit with 4 - BITS binary OUTPUT. (c) IC's for Decoding the Binary OUTPUT of Flip-flops to Decimal Output (d) 7- Segment Display to display the OUTPUT from 0-9. Block Diagram: 4 Bit Binary Flip-Flop 7-Segment Display Button Decoder Circuits CircuitsDIGIT ELECTRONICS
- 7. Draw a logic diagram for a 5-bit ring counter has an initial state 01011 and determine the waveform for each Q output during 5 clock pulses.F4 Using two flip-flops and basic gates, construct the circuit of the given state diagram below. Provide the following: State Table, Flip-flop equations, Circuit Diagram. Follow correct label names: Q0, Q1 – prev/present states D0, D1 – D-FF names X – input Y - outputThe waveforms in Figure 08 are applied to the 4-bit parity logic. Determine the output wave-form in proper relation to the inputs. For how many bit times does even parity occur, and how is it indicated? The timing diagram includes eight bit times. Q.21 Bit time Ao A1 A2 A3 FIGURE 08
- 3- Design a counter with a control input. When the input is high, the counter should sequence through three states: 10, 01, 11 and repeat. When the input is low the counter should sequence through the same states in the opposite order 11, 01, 10 and repeat.a) Draw the state diagram and state transition table.b) Implement the counter using D flip-flops and gates.a. Construct a synchronous 3-bit Up/Down counter with irregular sequence by using J-K flip-flops. The state diagram is shown below. Y = 1 00 010 110 Y =0 101 111 0, 011 100 001 b. Construct an asynchronous counter with a modulus of eleven by using J-K flip-flops. The counter should follow the straight binary sequence from 0000 through 1011. c. The counters are used in cascading in order to achieve the higher modulus operation. A certain application requires an overall modulus of 39,000 which can be achieved by placing the counters in cascading. You are requested to design a circuit for the said purpose by using 74HC161.1. Convert 95610 to hexadecimal. 2. Convert 1011.101 base 2 to decimal. 3. Convert 110100112 to decimal number system. 4. Convert 58610 to octal. 5. Convert 10111011012 to octal. (Our lesson is LOGIC CIRCUITS AND SWITCHING THEORY)
- 1)Design a 3-bit binary gray code up/down counter using J-K Flip Flops. Draw the state table, state diagram and draw the logic circuit.Construct an asynchronous counter with a modulus of eleven by using J-K flip-flops. The counter should follow the straight binary sequence from 0000 through 1011.answer the ff. tnxxxxxxxxxxx