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10/30/23, 3:08 PM Exercise 4 - ARM Data Processing Instructions: CSS 422 A Au 23: Hardware And Computer Organization Exercise 4 - ARM Data Processing Instructions Due Oct 30 at 11:59pm Points 4 Questions 8 Time Limit None Allowed Attempts 3 Take the Quiz Again Attempt History Attempt Time Score LATEST Attempt 1 192 minutes Ooutof4* * Some questions not yet graded @ Answers will be shown after your last attempt Score for this attempt: 0 out of 4 * Submitted Oct 30 at 3:08pm This attempt took 192 minutes. Question 1 Not yet graded / 0.5 pts 1. Under what conditions will the LSL instruction set the Z (zero) flag? Give an example. 2. Write an efficient assembly code that can implement the following expression with shifts. Xx=z/8-y value z EQU 80 value_y EQU 9 addr_x DCD 0 MOV RO, #value_z MOV R1, #value_y https://canvas.uw.edu/courses/1675565/quizzes/1921218 1/8

10/30/23, 3:08 PM Exercise 4 - ARM Data Processing Instructions: CSS 422 A Au 23: Hardware And Computer Organization Your Answer: operation is 0. 2. value_z EQU value_y EQU addr_x DCD MOV MoV LDR to R2 LSR ight shift operation SUB STR 80 1. The LSL instruction sets the Z (zero) flag when the result of the o Example: LSL R1, R1, #2, we are shifting the contents of R1 two positions to the left, Since R1 contains 0, after the shift operation, R1 will still contain zero => Z flag will be set. #value_z #value_y =addr_x ; Load the address of x in RO, #3 ; z / 8 is z / (273), use r RO, R1 ; Subtract y [R2] ; Store the result at addr_x Question 2 Not yet graded / 0.5 pts expression with shifts. x=z*10+y value_z EQU value y EQU addr_x DCD MOV MOV Your Answer: https://canvas.uw.edu/courses/1675565/quizzes/1921218 0 1. Why does Thumb2 instruction set architecture not support ASL (arithmetic shift left) and ROL (rotate left) instructions? 2. Write an efficient assembly code that can implement the following RO, #value z R1, #value_y 1. Thumb2 instruction set architecture does not support ASL (arithmetic shift left) and ROL (rotate left) instructions because of its design goal of 2/8

10/30/23, 3:08 PM Exercise 4 - ARM Data Processing Instructions: CSS 422 A Au 23: Hardware And Computer Organization improving code density and performance. The Thumb2 uses a mix of 16- bit and 32-bit instructions, and to fit these into a smaller space, some less commonly used instructions like ASL and ROL were excluded. Instead, Thumb?2 provides alternative instructions that can achieve the same results in a more efficient way like MOV and LSL. 2. value z EQU 8 value_y EQU 9 addr_x DCD 0 MOV RO, #value z MOV R1, #value_y LDR R3, =addr_x ; Load the address of x into R3 ; Implement z * 10 using left shift and addition (z*10=z*8 +z* 2) LSL R2,R0,#3 ;R2=z*8 LSL R4,R0,#1 ;R4=2z*2 ADD RO,R2,R4 ;R0=z*10 ADD RO, RO, R1 ; Add y to the result STR RO, [R3] ; Store the result at the address in x Question 3 Not yet graded / 0.5 pts Which assembly instruction is best suited to implement the following expressions? 1. r=y + 64x 2. r=z-Xxy Your Answer: https://canvas.uw.edu/courses/1675565/quizzes/1921218 3/8

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10/30/23, 3:08 PM Exercise 4 - ARM Data Processing Instructions: CSS 422 A Au 23: Hardware And Computer Organization 1. ADD, and LSL are suited because 64 = 2"6. example code: MOV RO, MOV R1, MOV R2, MUL RO, SUB RO, eg; LSL RO, RO, #6 ; Multiply x by 64, shift left 6 positions ADD RO, RO, R1 ; Addy to the result #x #y #z RO, R1 R2, RO 2. MUL and SUB are best suited (since we don't know the values of x and y). If asked to run in VisUAL, need to use other methods like loop conditions because MUL isn't supported in VisUAL. ; Load x into R@ ; Load y into R1 ; Load z into R2 5 Multiply x and y ; Subtract the result from z Question 4 Not yet graded / 0.5 pts value_x EQU addr_y DCD MOV LDR LDR https://canvas.uw.edu/courses/1675565/quizzes/1921218 1.y=y+x*32; value_x EQU addr_y DCD MOV LDR LDR 2. y=y+x*x; 5 RO, #value_x R1, =addr_y R2, [R1] RO, #value_x R1, =addr_y R2, [R1] 4/8

10/30/23, 3:08 PM value X addr_y value_x addr_y MOV LDR LDR MUL ADD STR value_x addr_y MOV LDR LDR LSL ADD STR Exercise 4 - ARM Data Processing Instructions: CSS 422 A Au 23: Hardware And Computer Organization Your Answer: EQU DCD RO, R1, R2, R2, R2, EQU DCD RO, R1, R2, R2, R2, EQU 8 DCD 5 MOV RO, #value x LDR R1, =addr_y LDR R2, [R1] LSL RO, RO, #5 ; Multiply x by 32 ADD R2, R2, RO ; Addthe resulttoy STR R2, [R1] ; Store the result back iny 2. since the question doesn't ask to run in VisUAL, | think using MUL is ok here. | would like to provide two methods because if this is to run in VisUAL, it's not possible because VisUAL doesn't support MUL. And here we know value of x which is 8 => x * x = 8 * 8 = 64, power of 2 => we can use LSL operation 8 5 #value_x =addr_y [R1] RO, R@ ; Multiply x by x R2, RO ; Add the result toy [R1] ; Store the result back in y #2 method using LSL 8 5 #value_x =addr_y [R1] RO, #3 ; Multiply x by itself (since x is 8 and 8*8 is 64) R2, RO ; Add the result to y [R1] ; Store the result back in y https://canvas.uw.edu/courses/1675565/quizzes/1921218 5/8

10/30/23, 3:08 PM Exercise 4 - ARM Data Processing Instructions: CSS 422 A Au 23: Hardware And Computer Organization Question 5 Not yet graded / 0.5 pts When R1 = 0x12348765 and R2 = 0x00000000, compute the contents of R2. 1. SBFX R2, R1, #4, #12 2. UBFX R2, R1, #3, #12 Your Answer: 1. SBFX R2, R1, #4, #12 = extracts a bit-field from R1, sign extends it to 32 bits, and writes the result to R2 R1 = 0x12348765 = binary number of R1 - 0001 0010 0011 0100 1000 0111 0110 0101 — bit number starts at #4 with length #12 = 1000 0111 0110 (the most significant bit in this range is 1) = Fill the rest of 32bits with 1 o 1111 1111 1111 1111 1111 1000 0111 0110 o 15 15 15 15 15 8 7 6 — R2 = 0xFFFFF876, R1 unchanged 2. UBFX R2, R1, #3, #12 R1 = 0x12348765 = binary number of R1 » 0001 0010 0011 0100 1000 0111 0110 0101 — bit number starts at #3 with length #12 = 0111 0110 0101 = Fill the rest of 32bits with 0 since this is a 0 extension o 0000 0000 0000 0000 0000 0111 0110 0101 . 0 0 0 0 0 7 6 5 https://canvas.uw.edu/courses/1675565/quizzes/1921218 6/8

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10/30/23, 3:08 PM Exercise 4 - ARM Data Processing Instructions: CSS 422 A Au 23: Hardware And Computer Organization — R2 = 0x00000765, R1 unchanged Question 6 Not yet graded / 0.5 pts Compute RO * 0.75, using ASR and ADD. Your Answer: Example code ASR R1, RO, #1 ; R1 = Re / 2, ADD RO, RO, R1 ; RO = RO + R1 => RO * 0.75 means taking three-quarters of RO, it is equivalent to adding h alf of the number itself (R@ / 2 in this case) to itself. => RO + (RO / 2) Question 7 Not yet graded / 0.5 pts 1. Why can TST and TEQ instructions affect the C flag? 2. Consider the addition instruction with flexible second operand Operand2, given below: ADD Rd, Rn, Rm, LSL #n It is desired to modify this instruction to the following new syntax: ADD Rd, Rm, LSL #n, Rn This new syntax can be called addition instruction with flexible first operand Operand1. What minimum change in the hardware architecture is required for the implementation of this instruction? Your Answer: 1. The TST and TEQ instructions in ARM assembly language can affect the C (Carry) flag because they perform bitwise operations (AND and https://canvas.uw.edu/courses/1675565/quizzes/1921218 7/8

10/30/23, 3:08 PM Exercise 4 - ARM Data Processing Instructions: CSS 422 A Au 23: Hardware And Computer Organization EOR respectively) on their operands1. The result of these operations can cause a carry in the case of TST or a borrow in the case of TEQ, which would affect the C flag 2. ADD Rd, Rn, Rm, LSL #n: adds the value in register Rn to the value in register Rm, shifted left by #n bits. The result is then stored in register Rd. -> Rd <- Rn + (Rm << n) Modify to ADD Rd, Rm, LSL #n, Rn -> Rd <- (Rm << n) + Rn Minimum Change: The instruction decoder would need to be updated to recognize and correctly interpret this new instruction format. The ALU would need adjustments to correctly execute these instructions. Question 8 Not yet graded / 0.5 pts Give two different instructions to clear register R5 to zero. You may not use any register other than R5. Your Answer: #1 method: Move the immediate value O into R5 MOV RS, #0 #2 method: Perform a bitwise exclusive OR on R5 with itself, since any number XORed with itself results in zero EOR R5, R5, RS Quiz Score: 0 out of 4 https://canvas.uw.edu/courses/1675565/quizzes/1921218 8/8

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