ECEN 248-504 Lab 4 Report

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Dec 6, 2023

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ECEN 248 - Lab Report Lab Number: 4 Lab Title: Simple Arithmetic Logic Unit Section Number: 504 Date: February 21 st , 2022 TA: Raiyan Chowdhury

Objectives: For this lab, I will continue to work with integrated circuits (ICs) and the breadboard. I will learn how to design and create a 4-bit Arithmetic Logic Unit (ALU). I will get to practice creating gate-level schematics and using them to wire the breadboard. This will help me wire the ALU since it requires a few components for the complete unit. The purpose of this lab is to create a 4- bit ALU to perform computations such as addition, subtraction, and bit-wise AND. Also, I will be able to learn and expand my knowledge in Two’s Complement arithmetic and multiplexers (MUX). Design: From the gate-level schematic that I made of the final ALU design, I was ready to start the setup of my DC power supply and the multimeter. You can see this design below in Figure 1. The question mark being the part of the overflow signal that I implement in Figure 6 (using (A 3 AND B 3 AND NOT(S 3 )) OR (NOT(A 3 ) AND NOT(B 3 ) AND S 3 )). Figure 1: Gate-level schematic for ALU design To start off the set up, I connected the red lead cable and the black lead cables of both the power supply and multimeter. Once both sets of equipment were set up, I turned them on and set the voltage range for the power supply. The higher limit of the range was set to 5V. I changed the voltage by turning the knob and made sure that the voltage that displayed on the power supply was the same as the one displayed on the multimeter.

Once set up was complete, it was time to power up the breadboard. I wired the red cable from the power supply to the red power rail and the black cable from the power supply to the blue power rail (ground). I was then able to start wiring my breadboard. I put a 74ALS08 (AND) IC, 74ALS86 (XOR) IC, 74HC283E (Full Adder) IC, and a 74CT257N (MUX) IC across the partition divisions. I connected the power and ground for all these chips, and I chose jumper wires to set up the inputs for A 0 -A 3 , B 0 -B 3, and C 0 -C 1 . I was able to wire everything correctly due to the reference pictures in the demo. These pictures demonstrated how to wire the full adder, the AND gate, and the MUX which allowed for an easy process to wire the complete ALU. For the full adder setup, you can see in Figure 2 that I had to use the XOR IC and I took those outputs and put them into the full adder as inputs with A 0 -A 3. Figure 2 : Full Adder Circuit Wiring I left the C out to use later for the overflow component of the ALU. I set up the SUM 0 -SUM 3 outputs to LEDs to double check if my full adder was wired correctly. I added 0111 (7) and 1000 (8) which gave me 1111 (15) which was correct. I also subtracted 1000 (8) from 0111 (7) which gave me 1111 (-1) which is also correct. Once I saw that my full adder was working properly, I took out the wiring to the LEDs and I left the sum outputs to wire into the MUX later. Next was the wiring of the AND chip which was the last wiring needed before the MUX. You can see in Figure 3 how I wired the AND gate.

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Figure 3: AND Gate Wiring After having the outputs of the Full Adder and the AND chips, I took those outputs and wired them into the 2:1 MUX. The outputs of the MUX then went out to the LEDs to show the output of the operation that was chosen. You can see the wiring of the MUX in Figure 4. Figure 4: MUX Wiring

After all the wiring was complete, I was able to wire the C 0 and test the R outputs. I was able to test the bit-wise AND, addition, and subtraction operations by changing the values for the C 0 and C 1 . When C 0 was off, the operation was AND. When C 0 was on and C 1 was off, the operation was addition. Finally, when C 0 was on and C 1 was on, the operation was subtraction. After testing a few values, I realized my ALU was complete, and I was able to test the values in the truth table with my ALU design. Results: After following the schematics and reference wiring pictures, I was able to create the complete 4- bit ALU using the breadboard. There were a few issues that I had with my full adder because if the sum outputs were connected to LEDs, I would get the correct output no matter the operation and no matter the inputs. However, once the full adder was wired with the MUX, the outputs from the MUX didn’t give me the correct outputs depending on the operation and the inputs. I would receive the correct output with 3 + 4, but I didn’t receive the correct output if I did 7 + 8. I couldn’t figure out a solution to this problem. I debugged by unwiring the MUX and testing my full adder twice. The first time, the full adder didn’t work normally, but the second time it gave the correct outputs again. Once the full adder was working again, I rewired the MUX, and I was able to fill out the truth table as you can see in Table 1. Conclusion: To complete this lab, I was able to use my knowledge on how to properly set up the DC power supply, the multimeter, and the breadboard. Using the equipment, I was able to power up the ICs with proper wire management and create the complete ALU. From this lab, I learned how to properly wire the ALU using different components that were used in other experiments. I also learned how to wire a MUX since that was the main component in this experiment because it was used to change the operation. I was also able to debug my breadboard and continue the experiment once my outputs were correct to fill out the truth table. One last thing I learned was how to wire the overflow of the ALU since a different method had to be used to wire this part of the ALU. This is because the C 2 of the full adder was unable to be used for the overflow, so the expression stated before was used to help that problem.

Post-lab Deliverables: 1. Observe and fill in Table 1. Both A and B are two’s complement numbers. The result should be a 4-bit binary number. Determine whether overflow occurs or not. Table 1: Truth Table for Final ALU Design c 0 c 1 Operation A B Result Overflow 0 0 AND 0100 0110 0100 or 1 0 0 1 AND 0110 1101 0100 or 1 0 1 0 ADD 0100 0110 1010 1 1 0 ADD 0100 1101 0001 0 1 0 ADD 1101 1001 0110 1 1 1 SUB 0100 0111 1101 1 1 1 SUB 0110 1001 1101 0 To double check the values I received from my ALU outputs, I calculated the addition, subtraction, and bit-wise AND by hand. I also calculate the overflow by hand, and it matched with my truth table which is what should be expected. 2. Determine the maximum gate delay through your final ALU circuit assuming each gate has a delay of 1 unit. Highlight the critical path on the gate-level schematic. I was able to find that the maximum gate delay would be 18 units. You can see the path in Figure 5 . This includes the complete ALU with the overflow portion imbedded as well. I tested this with an input of 0011 + 0111 which gives an answer of 1010 which is also overflow. You can see we get this value from the ALU since overflow, R 3 , and R 1 are all on.

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Figure 5: Maximum Delay Path

3. Please design the overflow detecting unit in Figure 6. You can use all available signals except the signals inside the chip package. Show your process and draw a gate-level schematic. Figure 6: Overflow Design