2020 annotated EOC Chapter 4_final

What is the result of the following FAL instruction? Input L1 Loo a. O b. O C. A HE e. Ladder logic program FAL FILE ARITH/LOGICAL Control Length Position Mode Destination Expression None of the choices (EN) (DN) Incremental (ER) #N7:101 R6:2 6 0 0 N7:100 On successive transitions, data will be copied from N7:100 into the next position in the file #N7:101 until N7:106 is reached Once input A becomes true, data will be copied #N7:101 into the next address of N7:100 O d. On successive transitions, data will be copied #N7:101 into the next address of N7:100 Once input A becomes true, data will be copied six times from #N7:100 into the word #N7:101

Task 1: You are to design a 4-bit arithmetic unit that consists of a 4-bit adder/subtractor circuit. The arithmetic unit takes as inputs two 4-bit numbers (A and B) and one control input (M) add/subtract selector that selects the type of operation the unit will perform. When the input control is ‘0’, the input numbers are added. When it is set to ‘1’, the two input numbers are subtracted (A - B)

Please help me fill in the worksheet. And for the second part of the worksheet you have to make that circuit on TinkerCAD, with leds, etc.

Logic circuit Multiplexer In this question I used same question for two different cell scheme types First one I used up to down cell scheme like 0 4. 12 8 1. 5. 13. 9 3. 7. 15. 11 2 8. 14. 10 Function is €m(0,5,6,8,9,10,14) I got in the letter below I0=B’ Means B complement I1=A’B+AB’ I2=A+B I3= 0 But second k map cell scheme I used like this right to left for the same function 0. 1. 3. 2 4. 5. 7. 6 12. 13. 15. 14 8. 9. 11. 10 But I got different answers for the same function I0=A’B’. I1=A’B+AB’ I2=AB’. I3 = A’+B’ Only i1 I got the same but isn’t which ever cell scheme you use the answer shouldn’t be different right or I do it wrong please look the picture carefully give brief explanation where did I understand wrong

Signed integers are represented in two's complementary formats. Does the same arithmetic hardware (or algorithm) work exactly the same between a. Unsigned addition and signed addition? b. Unsigned subtraction and signed subtraction? c. Unsigned multiplication and signed multiplication(if the product obtained the same length as the operands)? d. Unsigned division and signed division? Please give your answer as "true" or "false" for the above 4 questions.

Q1. Convert following numbers in given radix system: a. (697)10 into Octal and Hexa decimal b. (2D9)16 into Decimal and Octal Q2. Using two's complement representation, solve: a. 101110001 – 1111111001 b. 1010101010 – 1010010101 Q3. Perform following arithmetic operations: a. (6767)10 + (3592)10 using BCD b. (C7C)16 - (B0E)16 using 16's complement Q4. A code 1011011 needs to be sent to the receiver. Using, hamming code find out the code- word and the mechanism to check the corrected data when error occurred at 4th bit. (Assumptions: Right to Left with Odd Parity) Q5. (a) Convert the following logic gate circuit into a Boolean expression, writing Boolean sub-expressions next to each gate output in the diagram: A (b) Realise Ex-OR gate using universal gate? Q6. Implement and simplify f (A, B, C, D) = E(1,3,5,8,9,11,13,15) using K-map?

The numbers from 0-9 and a no characters is the Basic 1 digit seven segment display * .can show False True In a (CA) method of 7 segments, the anodes of all the LED segments are * "connected to the logic "O False True Some times may run out of pins on your Arduino board and need to not extend it * .with shift registers True False

Identify what type of Finite State Machine would be required to implement the given sequence: =01011100100010010010 00000000010000001001 Mealy FSM Moore FSM OShannon FSM

Please answer in typing format

Which of the following statements is TRUE about the following code segment?

c) Look-Up Table ROM values for a Distributed Arithmetic (DA) scheme to implement the following expression is provided in Appendix 1: I = 2x xo +4xx₁ +2xx₂ + 4xx3 Undertake a check calculation with the following values of x (in8-bit 2's complement) and comment on the calculated result. Data XO X1 X2 X3 decimal -10 -20 30 40

Procedure: You are to design a 4-bit arithmetic unit that consists of a 4-bit adder/subtractor circuit. The arithmetic unit takes as inputs two 4-bit numbers (A and B) and one control input (M) add/subtract selector that selects the type of operation the unit will perform. When the input control is ‘0’, the input numbers are added. When it is set to ‘1’, the two input numbers are subtracted (A - B). Question: Two 4-bit Adder/Subtractor Circuit: Design and construct a 4-bit adder/subtractor circuit. Draw the produced circuit.

QUESTION 1 You have used DEBUG to unassemble the following instructions. -U 0100 0108 1369:0100 B84365 MOV AX, 6543 1369:0103 BB3394 MOV BX, 9433 1369:0106 F7E3 DEC BX 1369:0108 CD21 INT 21 The last byte of the instruction loaded at address 0106 is stored in address. 0100 0106 0107 0108

Logic circuit Design combinational logic circuit that takes 7 bit numbers and an input and output will be the reverse of this bits from right to left to the first one including one and remaining of the bits will be the same example input 0011000 output 0010111 Can you draw it’s logic circuit in detail not theory answer and if we can solve this question multiplexer