ECEN 471- Lab4-Ward

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Apr 3, 2024

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ECEN 471 Lab 4 Hailey Ward Section: 502 UIN: 430004826 Due: 2/28/24

Procedure: In this lab, we investigated the effects of capacitive load on the loop stability of a low-dropout (LDO) regulator. The LDO circuit, consisting of an LM741 op-amp and a 2N3906 PNP transistor, was built on a breadboard and tested with different capacitive loads (CL = 33pF, 100pF, 200pF, 500nF). We observed the transient responses of the output voltage (VOUT) when a pulse was applied to the reference voltage (VREF) using an oscilloscope. The experimental results were compared with LTSpice simulations, showing similar trends. Larger load capacitances resulted in slower settling times and potential stability issues, highlighting the importance of carefully choosing the output capacitor for LDO designs. PreLab: 1. Simulate LDO in LTSpice Figure 1: LDO regulator with CL = 1pF 2. Calculate DC output Voltage and verify with simulations. 𝑉 𝑜?? = 𝑉 𝑟?? (1 + 𝑅 1 𝑅 2 ) = 5v 𝑉 𝑜?? = (2. 5?)(1 + 10𝑘Ω 10𝑘Ω )

Figure 2: .OP Report of LDO regulator with CL= 1pF - The DC Operating report shows that the Vout = 4.998v 3. Set Vref source to pulse Figure 3: Transient response with Vref set to pulse and CL= 1pF 4. Redo transient simulations with CL as 1pF, 10pF, 100pF, and 1nF a. CL = 1pF

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Figure 4: Transient response with Vref set to pulse and CL= 1pF b. CL = 10pF Figure 5: Transient response with Vref set to pulse and CL= 10pF c. CL = 100pF Figure 6: Transient response with Vref set to pulse and CL= 100pF d. CL = 1nF Figure 7: Transient response with Vref set to pulse and CL= 1nF - As the capacitance decreases there is more oscillation. This means that as the capacitance value decreases the circuit becomes more unstable. Lab: 1. Breadboard the LDO circuit a. Observe settling time in the oscilloscope

Figure 8: LDO regulator breadboarded - The settling time for the circuit with the capacitor at 33pF was around 25μs. 2. Provide a pulse at Vref a. Observe the output voltage Figure 9: (Breadboarded circuit) Transient response of Vout. Vref = pulse. CL = 33pF

3. Repeat 2 with CL = 33pF, 100pF, 200pF, and 500pF a. CL = 33pF Figure 10: LDO regulator breadboarded CL = 33pF - The output voltage stepped from 4.8v to 5.2v. - The settling time is around 25μs. b. CL = 100pF Figure 12: LDO regulator breadboarded CL = 100pF - The output voltage steps from 4.81v to 5.19v.

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- The settling time is over 50μs. c. CL = 200pF Figure 13: LDO regulator breadboarded CL = 200pF - Output voltage steps from 4.81v to 5.19v. - The settling time is over 50μs. d. CL = 500pF Figure 14: LDO regulator breadboarded CL = 500pF - Output voltage steps from 4.84v to 5.2v. - The settling time is over 50μs. 4. Do the oscilloscope responses match the simulations? If not, why? - While we had to use different capacitance values for the oscilloscope responses both the simulations and oscilloscope responses had the same output voltage, but the settling time was 5 times shorter for the simulations. For the capacitance of 100pf, 200pF, and 500pF I set it at a low frequency so then there is not enough time to see complete settling time. Although you can still see that it takes significantly longer to settle than the simulations

Conclusion: The lab experience was challenging due to equipment alignment issues, requiring frequent restarts throughout the session, which impeded progress. Despite these difficulties, I was able to complete the lab and obtain accurate measurements. The objective was to demonstrate the effect of increasing capacitance on output voltage oscillation, which was successfully achieved. The settling time was a key indicator, showing an increase as capacitance increased. In some cases, the frequency was too low to observe settling time. A comparison between simulations and lab measurements revealed close agreement, with the exception of longer settling times in the lab, likely due to additional factors affecting real-world measurements. Overall, the lab provided valuable insights into LDO behavior under varying load conditions