ECE230L_Lab02

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Boise State University *

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230L

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Electrical Engineering

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Apr 3, 2024

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Boise State University Electrical and Computer Engineering Department EE230L: Digital Systems Laboratory Lab 2: NAND-only Logic Networks Project Group: Team 31 Team Members: Maten Karim, Damian Guzman Experiment Date: 01/30/2024 Report Due: 02/02/2024

Title of Lab ECE 230L Page 2 of 9 1 Objective In this lab, we utilized the 2-input NAND gate and proved why it is considered a “universal” gate. Understanding the importance of NAND gates was done by comparing the block design and simulations of the AND and OR gates versus the NAND gates. This was represented in both Vivado and the NAND gate was replicated on a protoboard. 2 Content Overview The first step was to create a block design of the logic by using AND, OR, and INV gates. Then, the same logic was created using only 2-input NAND gates. NAND gates reduce chip counts because logic circuits using AND gates and OR gates can have multiple logic chips while a logic circuit utilizing 4 or fewer NAND gates will need only 1 logic chip. From there, a simulation was done and the waveform created helped compare the differences between the two different block designs. The final step was to replicate the NAND gate only block design with a protoboard and verify the expected outcomes are correct. 2.1 Content In figure 1, the 2 block designs are represented with switches SW3, SW2, SW1, and SW0 and the leds are LD0, LD1, and LD2. There is an XNOR gate with an output of LD2 to compare the LD0 (which is the logic circuit for the AND, OR, and INV gates) to the LD1 (the NAND only gate logic circuit). The logic trying to be implemented for LD0 is: 𝑓 = ( ? ∗ ~ ? ) + ( ? ∗ ? ) The logic for LD1 is: 𝑓 = ~(~( ? ∗ ~ ? ) + ~( ? ∗ ? )) Figure 1: Block Design

Title of Lab ECE 230L Page 3 of 9 In figure 2, the simulation represented by the waveform verifies the outputs. It shows the inputs of all 4 switches, and the output of each led. The test is being ran through 16 different combinations (0-9 and A- G). Figure 2: Waveform 2.2 Results The NAND gates are proven to be universal as the outputs produced by it matches the block design of the AND, OR, and INV gates. The expected results match the actual results. 3 Part II Content Overview For the second part, the NAND gate only logic circuit is put to the test on a protoboard. A 74HC00 chip which contains 4 NAND gates was used to prove the logic.

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Title of Lab ECE 230L Page 4 of 9 3.1 Content Connect the ground and power wires to ensure the board is working. Then, connect the wires from the switches to the correct NAND gates and implement the block design created in part 1. Power the board on and test the inputs to ensure the results are correct as expected. Figure 3: 0010 | Output = 0

Title of Lab ECE 230L Page 5 of 9 Figure 4: 0011 | Output = 1

Title of Lab ECE 230L Page 6 of 9 Figure 5: 1011 | Output = 1

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Title of Lab ECE 230L Page 7 of 9 Figure 6: 1111 | Output = 1

Title of Lab ECE 230L Page 8 of 9 3.2 Results When switching on SW3 or “A”, the led turns on. When switching on SW1 & SW0 or C & D, the led turns on. The end result showed that SW3 has to be on OR SW1 & SW0. The actual results matched the expected results. 4 Conclusions The NAND gate is very versatile and can be used in many situations. An AND gate and an inverter makes a NAND gate. There was an issue when implementing the NAND gate since the switch SW2 had to be inverted. This was solved by connecting SW2 to both inputs of a NAND gate. Overall this lab was very intriguing and the hands-on portion was fun. Being able to actually see what we created from Vivado on a protoboard helped us better understand how the NAND gate works. The topic of Sum-of-Products from lecture was better understood because of this lab.

Title of Lab ECE 230L Page 9 of 9 Appendices Please include Verilog test benches, chip pin outs, circuit schematics … etc . not already included in the “Content” sections. Test benches should be formatted as a fixed-font (e.g. “Courier New”) to resemble what is seen in a typical text editor. You may shrink the size of this font down to 6 or 8 pts so the test bench better fits on a page without word-wrapping. Example: 4.1 NAND-Only Implementation Verilog Test Bench `timescale 1ns / 1ps module lab03_tb( ); // test bench has no inputs or outputs reg [3:0] switches; // Four switch values to drive the design wire [2:0] leds; // Four LED values returned from design reg [2:0] e_led; // Four expected LED values calculated by TB integer i; // A loop index your_design_wrapper_name dut( // Instantiate your design .LD0(leds[0]), // Attach your output port LD0 to leds[0], etc. .LD1(leds[1]), .LD2(leds[2]), .SW0(switches[0]), // Attach your output port SW0 to switches[0] .SW1(switches[1]), .SW2(switches[2]), .SW3(switches[3])); // End of design instantiation function [3:0] expected_led; // Function to calculated expected values input [3:0] swt; // Function takes four input values begin expected_led[0] = <your edits would be shown here> ; // Your comment on what this is expected_led[1] = <your edits would be shown here> ; // Your comment on what this is expected_led[2] = expected_led[1] ~^ expected_led[0]; // Comparing the SOP and NAND-only equations end endfunction // Step through switches = 0b’0000, 0b’0010, 0b’0100, 0b’0110, ... // Note: this does not test output when SW0 = 1 initial // An initial block runs once start to finish begin for (i=0; i<16; i=i+1) // i = 0, 2, 4, 6, ... , 14 begin #20 switches = i; // wait 20ns, set switches to binary of i #10 e_led = expected_led(switches); // wait 10ns, call func end #50 $finish; end endmodule

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