ECE230L_Lab7

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Boise State University *

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230L

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Electrical Engineering

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Apr 3, 2024

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Boise State University Electrical and Computer Engineering Department EE230L: Digital Systems Laboratory Lab 7: BCD Timer w/ Display Project Group: Team 31 Team Members: Maten Karim, Damian Guzman Experiment Date: 03/12/2024 Report Due: 03/15/2024

Title of Lab ECE 230L 1. Objective In this lab, we are creating a 4-digit BCD timer that will be resettable. D flip flops and BCD adder blocks will be used to implement the timer and we will display minutes and seconds utilizing a seven-segment display. 2. Content Overview In this lab, we are introduced to 4 new IP block components that we will need to properly implement the BCD timer. The first is the slice block which is the opposite of the concatenation block. It takes in an n-bit input and will display the output based on the criteria given. The second is the clk_divider which controls the rate of the clock signal. The third is the D flip flop which has the enable and reset inputs as well as the clock and the D input. The final new component is the multiplexer or MUX which takes in multiple input lines and outputs only one of them using a control signal. By combining these new IP components, and the concepts we utilized in the last lab, we can create the BCD timer by first creating the logic design and then testing through simulations. 2.1. Content In figure 1 below, the block design is shown for the BCD timer with a display. The previous mentioned IP components can all be seen being correctly utilized. The simulation waveforms in figure 2 and figure 3 prove this block design functions properly. Figure 1: BCD Timer w/ Display Block Design In figure 2 below, the simulation waveform shows the specific time of 5:59. It can be seen, that when the next second comes, and the timer is now at 6:00, the minutes and seconds change accordingly. The seconds are reset to 0 in both the ones and tens place, while the ones place of the minutes is increased to 6. Page of 2 5

Title of Lab ECE 230L Figure 2: BCD Timer w/ Display Simulation Waveform (5:59 – 6:00) In figure 3 below, we have another snippet of the simulation waveform, but this shows the specific change from 9:59 to 10:00. As shown in Figure 2 above, the ones of the minutes, tens of the seconds, and ones of the seconds all reset to 0 while the tens of the minutes increment to 1. Figure 3: BCD Timer w/ Display Simulation Waveform (9:59 – 10:00) 2.2. Results Page of 3 5

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Title of Lab ECE 230L The simulation waveforms prove our design works correctly. When the seconds hit 59 they will reset to 0 and increment the minutes to the next value. This logic works up until the timer is at 59:59. We can then use the same logic as we get closer to the hours. Question 1: How does a dff work? Explain when the value inside the flip flop changes and how the dinput and q output differ. - A D-Flip Flop works by sampling the D input at each clock event and transferring that value to the Q output. The Q output remains constant between clock events, regardless of any changes at the D input during that time. This makes the D-Flip Flop an essential component in digital circuits for storing and transferring data synchronously with a clock signal. Question 2: What condition are you checking to generate the select signal of the multiplexer? I.e. What signals are you checking and what logic are you using to implement the select input of the multiplexer to load a ‘0’ on the dff? - The multiplexer’s sel input has it so when it is a 0 it will output the a input and when its 1 it will output the b input. The b input is set to 0 so when the sel is 1, it will load a 0 into the dff. The logic going into the sel is two slice blocks and the c_out of the second’s ones place adder all going into a 3-bit AND block. The two slice blocks check if the number is 5 (one slice block checks if the 4’s place bit is 1 and the other slice block checks if the 1’s place bit is 1). The output of the AND gate will only be 1 when all the inputs are 1, which if the carryout of the ones place is 1, this means the number just hit “10” and if both slice blocks are 1, then the tens place is already at 5. This means the number is about to hit 60, so the dff gets a 0 loaded into it to reset the whole thing. Question 3: Why did we want to set the xup_clk_divider to SIZE = 10 for this design (this is the clkoutsignal you added to your waveform)? Explain what would happen in simulation if we had a one second clock as is typical for a timer. - A clock divider takes an input clock signal and divides its frequency by a certain factor, producing a slower clock signal as output. This is crucial in designs where different parts of the system require clocks at different frequencies. 2.3. Conclusions We learned how to properly implement a BCD timer with a reset capability. Using the new IP components did get confusing and we ran into issues when resetting the seconds at 59. Our system would keep going to 99 and then reset to 0 but this was incorrect since the tens place of the seconds need to reset when it goes from 5 to 6. We learned a little bit about D flip flops in lecture but this lab helped us really understand it even more. Overall, this lab was very humbling and shows we need to prepare even more for the next labs as I can only assume they will get harder. Page of 4 5