ECE230L_Lab03 (1)

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Boise State University Electrical and Computer Engineering Department EE230L: Digital Systems Laboratory Lab 3: Full and 4-bit Adder Project Group: Team 31 Team Members: Maten Karim, Damian Guzman Experiment Date: 02/06/2024 Report Due: 02/09/2024

Lab 3: Full and 4-Bit Adder ECE 230L Page 2 of 8 1 Objective For this lab, we are creating a 1-bit full adder and using it to create a 4-bit adder. We are implementing topics from lecture such as adder design and the resources utilized. 2 Content Overview A full adder is a logic circuit with three one-bit inputs which will be x, y, and c_in and two one-bit outputs which will be s and c_out. The x and y values are what we are adding together and the c_in value will be the carry-in bit. The s output is the least significant value in the bit number and the c_out value will be the most significant in the sum. Binary addition is similar to decimal addition, but the columns will be in powers of 2 and not 10. To create a 4-bit adder, you need to connect 4 of the 1-bit full adders together. The design will have a ripple effect as they are connected together. This 4-bit adder can take two 4-bit numbers for x and y and will produce a 5-bit number. 2.1 Content Part 1 of the lab requires to create the block design for the 1-bit full adder. By using XOR, AND, and OR gates, the block design could be implemented as can be seen in figure 1 below. The x and y inputs are first connected to the first XOR gate, while the c_in is connected to the second XOR gate. The first XOR gate will now be connected to the second XOR gate which will produce the s output. From here, connect (x,y), (x,c_in), and (y,c_in) each to their respective AND gates. The outputs of each AND gate will be connected to the inputs of the OR gate which will then output the result of c_out, or the carry-out value. Figure 1: 1-Bit Full Block Design

Lab 3: Full and 4-Bit Adder ECE 230L Page 3 of 8 The waveform simulation of the 1-bit full adder shows that our design and test bench were correctly implemented. Both the s and c_out outputs match with the expected results. The example shown in figure 2 below depicts inputs of x = 0, y = 0, and c_in = 1. These inputs give a result of s = 1 and c_out = 0. The test bench that produced the simulation waveform below is found in the appendix as labeled 5.1 1-Bit Full Adder Implementation Verilog Test Bench. Figure 2: 1-Bit Full Simulation Waveform 2.2 Results A 1-Bit Full Adder successfully adds two inputs and produces outputs of s (the least significant value) and c_out (the most significant value). The XOR gate was able to add the two input values and have an output representing the sum and carry-out values. The two 1-bit input values successfully produced a 2-bit value. 3 Part II Content Overview For part 2, the 1-Bit Full Adder created in part 1 will be used to create a 4-Bit Binary Adder. To create a 4- bit adder, you need to connect 4 of the 1-bit full adders together. The design will have a ripple effect as they are connected together. This 4-bit adder can take two 4-bit numbers for x and y and will produce a 5- bit number. 3.1 Content In Figure 3 below, there are 8 inputs from SW7 through SW0 and a center button labeled BTNC. Figure 3: 4-Bit Adder Block Design

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Lab 3: Full and 4-Bit Adder ECE 230L Page 4 of 8 Figure 4 below depicts the truth table for the LUT3 block named s_INST_0. Since the system outputs a “1” when there is an odd number of “1” inputs, this proves that we are using the XOR gate correctly. This correctly explains the behavior of a combinational logic circuit. Figure 4: 4-Bit Adder Truth Table In Figure 5, there are 3 separate examples adding two 4-bit binary numbers together. The left-most example proves that the system correctly added together an x value of 0 (0000) and a y value of 5 (0101) which came to be 5 (0101). The middle example shows if x = 1 (0001) and y = 9 (1001). The right-most example proves the theory that the 4-Bit Binary Adder can add 2 4-bit binary numbers to produce a 5-bit output. The x = 8 (1000) and y = 9 (1001) which gives a result of 17 (10001). The waveforms below is produced by the test bench in the appendix labeled 5.2 4-Bit Binary Adder Implementation Verilog Test Bench. ***Unfortunately we did not take great photos so I understand we will get docked for not showing the output values and not taking full pictures. We were on a time crunch and I have no way of getting the lab files.*** 0000 + 0101 = 0101 0001 + 1001 = 1010 1000 + 1001 = 10001 5 10 17 Figure 5: 4-Bit Adder Behavioral Simulation

Lab 3: Full and 4-Bit Adder ECE 230L Page 5 of 8 In figure 6, the waveform is a little different from the waveforms from figure 5. This is because the timing waveform shows a more detailed view of the logic design, and takes into account the time delays to actually run the process whereas a behavioral waveform shows a more abstract view. The time delays can be seen in Figure 7. The waveform below is produced by the test bench in the appendix labeled 5.2 4-Bit Binary Adder Implementation Verilog Test Bench. Figure 6: 4-Bit Adder Timing Waveform 3.2 Results Question 1: “How many LUTs and IO are used in your implemented design and how many LUT’s and IO are available in the FPGA device? - There are 7 LUTs and 7 IOs in our implemented design and the FPGA device has 20800 LUTs and 106 IOs available. Question 2: “ What do you notice about this simulation that is different from the one run in Step 3? Can you explain the differences?” - The main difference between the behavior simulation and the timing simulation is that the timing simulation has a difference in the output where it is “computing” the answer. This difference shows because the 4-Bit adder uses a lot more power and that space is pretty much the time it takes to compute the output. Figure 7 below shows the spaces between the outputs. The waveform below is produced by the test bench in the appendix labeled 5.2 4-Bit Binary Adder Implementation Verilog Test Bench. Figure 7: 4-Bit Adder Timing Waveform (zoomed in on x = 8 & y = 9) Question 3: “What values are you adding and do the results make sense? How is the combination of sum and c_out used to explain the correct answer?” - We are adding x which is 8 and y which is 9 and the carry-out is 1. This makes sense because the carry- out is the result of 1 + 1 which will result in 10 (the “1” is the extra or carry -out). The sum is the result of adding the bits and the carry out is the extra position that is produced which in this case is 1. The sum of 1000 + 1001 = 0001 which is the sum. The carryout and the sum will equal 10001.

Lab 3: Full and 4-Bit Adder ECE 230L Page 6 of 8 4 Conclusions An XOR gate can be used to add binary numbers together. A 1-bit full adder will add together 2 1-bit inputs and output a 2-bit binary number. Using 4 1-bit full adders, you can create a 4-bit Binary Adder which can then add together 2 4-bit numbers and able to output a 5-bit number. We ran into trouble when making logic design for the 1- bit full adder because we didn’t think of using 2 XOR gates for the “s” output. Other than that specific part, we ran into trouble with smaller things using Vivado such as not wrapping the classes correctly and correctly implementing the test benches. Overall, this lab was very useful and helped our understanding of binary addition that we learned in lecture.

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Lab 3: Full and 4-Bit Adder ECE 230L Page 7 of 8 5 Appendices 5.1 1-Bit Full Adder Implementation Verilog Test Bench `timescale 1ns / 1ps module lab03_part_I_tb( ); // test bench has no inputs or outputs reg x, y, c_in; // Registers to drive the design. wire s, c_out; // Wires to carry output signals. reg expect_sum, expect_carry; // Expected values. Lab03_wrapper dut( // Instantiate your design .x(x), // Attach your module ports to testbench signals. .y(y), .c_in(c_in), .s(s), .c_out(c_out) ); // End of design instantiation task expected_output; // Task to calculate expected values input x, y, c_in; // Task takes three input values output e_s, e_cout; // Task generates two output values begin e_s = c_in ^ (x ^ y); // Enter equation for Expected sum e_cout = (x & y) | (x & c_in) | (y & c_in); // Enter equation for Expected carry-out end endtask // Step through all combinations of input switches initial // An initial block runs once start to finish begin for (integer i=0; i<8; i=i+1) // i = 0, 1, 2, ... , 7 begin #20 x = i[0]; y = i[1]; c_in = i[2]; // wait 20ns, set input values #10 expected_output(x, y, c_in, expect_sum, expect_carry); // wait 10ns, call task end #50 $finish; end endmodule 5.2 4-Bit Binary Adder Implementation Verilog Test Bench `timescale 1ns / 1ps module lab03_part_II_tb( ); // test bench has no inputs or outputs reg [3:0] x,y; // Eight switch values to drive the design reg c_in; // Pushbutton wire c_out; // Overflow wire [3:0] sum; // LED values returned from design reg expect_carry; // LED4 for overflow reg [3:0] expect_sum; // Four expected LED values calculated by TB lab03_part2_wrapper dut( // Instantiate your design .LD0(sum[0]), // Attach your output port LD0 to leds[0], etc. .LD1(sum[1]), .LD2(sum[2]), .LD3(sum[3]), .LD4(c_out), .SW0(y[0]), // Attach your input port y[0] to SW[0] .SW1(y[1]), .SW2(y[2]), .SW3(y[3]), .SW4(x[0]), .SW5(x[1]), .SW6(x[2]), .SW7(x[3]), .BTNC(c_in) ); // End of design instantiation function [4:0] expected_sum; // Function to calculate expected values input [3:0] x,y; // Function takes two four-bit inputs input c_in; begin expected_sum = y + x + c_in; // Calculate the sum end endfunction // Step through all combinations of input switches

Lab 3: Full and 4-Bit Adder ECE 230L Page 8 of 8 initial // An initial block runs once start to finish begin c_in = 0; for (integer i=0; i<256; i=i+1) // i = 0, 1, 2, 3, ... , 255 begin #20 {y,x} = i; // wait 20ns, set switches to binary of i #10 {expect_carry,expect_sum} = expected_sum(y,x,c_in); // wait 10ns, call func end #50 $finish; end endmodule

ECE230L_Lab03 (1)

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