ECE230L_Lab01

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Boise State University *

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230L

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Electrical Engineering

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Apr 3, 2024

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Boise State University Electrical and Computer Engineering Department EE230L: Digital Systems Laboratory Lab 1: Verilog Logic and XOR Checking Project Group: Team 31 Team Members: Maten Karim, Damian Guzman Experiment Date: 01/23/2024 Report Due: 01/26/2024

Lab 1: XOR Checking ECE 230L Page 2 of 5 1 Objective In this lab we used OR gates and XOR gates to expand on what we learned from the tutorial. We used the OR gates to check whether two signals are the same or not. 2 Content Overview To make our logic work, we used Verilog notation to write out the equations of our seven outputs. We had four inputs, 3 switches and one center button. We inputted the Verilog equations into the testbench and correctly labeled them. 2.1 Content The block design represented in figure 1 below shows how the various AND, OR, and XOR gates work together. It depicts the use of 5 AND gates, 4 INV gates, 3 OR gates, 3 XOR gates, and 1 XNOR gates. The 4 inputs to the left are the switches and the 7 outputs to the right are the leds. Figure 1: Block Design In figure 2 below, we manually entered in the Verilog equations within our testbench. We did this to ensure the outputs are correct and are functioning properly. The variable names needed to be correct in order for the outputs to respond correctly.

Lab 1: XOR Checking ECE 230L Page 3 of 5 Figure 2: Testbench In figure 3 below we have a snippet of the waveform that was produced from the block design and testbench. It shows our inputs and outputs are matching the expected results. Figure 3: Waveform

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Lab 1: XOR Checking ECE 230L Page 4 of 5 2.2 Results The switches we created in the block design are working properly as the waveform above shows. The values we produced matched the expected values given to us. Question 1 : What is the significance of the XNOR gate? What does this show about the logic connected to the inputs of this gate? The XNOR gate’s function is true when the inputs are even. The inputs of the XNOR gate in our lab are LD0 and LD5. When both LD0 and LD5 are “0” or “1”, LD6 will be “1” or true. The outputs LD0 and LD5 are synchronized and are always false until SW0, SW1, and SW2 are all true. 3 Conclusions We learned that the XNOR gate functions the exact opposite of an XOR gate which means the outputs are 1 when the inputs are even. Everything went smoothly other than knowing which notation takes precedence over the other when writing our Verilog equations. It was interesting working with an output that is reliant on other outputs. It was also very informative seeing how an XNOR gate actually functions in a block design since it was hard to conceptualize in class.

Lab 1: XOR Checking ECE 230L Page 5 of 5 4.1 Lab01 Verilog Test Bench `timescale 1ns / 1ps module lab01_tb( ); // test bench has no inputs or outputs reg [2:0] switches; // Switch values to drive the design reg btnc; // Pushbutton wire [6:0] leds; // LED values returned from design reg [6:0] expect_led; // Expected LED values calculated by TB integer i; // A loop index lab01 dut( // Instantiate your design .LD0(leds[0]), // Attach your output port LD0 to leds[0], etc. .LD1(leds[1]), .LD2(leds[2]), .LD3(leds[3]), .LD4(leds[4]), .LD5(leds[5]), .LD6(leds[6]), .SW0(switches[0]), // Attach your output port SW0 to switches[0] .SW1(switches[1]), .SW2(switches[2]), .BTNC(btnc)); // End of design instantiation function [6:0] expected_led; // Function to calculated expected values input [2:0] swt; input btc; // Function takes four input values begin expected_led[0] = swt[0] & swt[1] & swt[2]; expected_led[1] = swt[0] | swt[1] & btc; expected_led[2] = swt[0] ^ swt[1]; // You will need to enter the remaining equations expected_led[3] = swt[0] ^ swt[1] ^ swt[2]; expected_led[4] = swt[0] & swt[1] | swt[1] & swt[2] | swt[0] & swt[2]; expected_led[5] = ~(~swt[0] | ~swt[1] | ~swt[2]); expected_led[6] = leds[5] ~^ leds[0]; end endfunction // Step through switches = 0b’0000, 0b’0010, 0b’0100, 0b’0110, ... // Note: this does not test output when SW0 = 1 initial // An initial block runs once start to finish begin #10 btnc = 0; for (i=0; i<8; i=i+1) // i = 0, 1, 2, ... , 7 begin #20 switches = i; // wait 20ns, set switches to binary of i #10 expect_led = expected_led(switches,btnc); // wait 10ns, call func end #10 btnc = 1; for (i=0; i<8; i=i+1) // i = 0, 1, 2, ... , 7 begin #20 switches = i; // wait 20ns, set switches to binary of i #10 expect_led = expected_led(switches,btnc); // wait 10ns, call func end #50; $finish; end endmodule

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