Lab 6 Schematic Entry - Counters
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1
Programmable Logic Devices
With the
Altera Cyclone IV FPGA
Lab 6 – Counter Design
Students use the Quartus II IDE to design a 3-bit binary counter on the Cyclone IV FPGA. A single bit mode control is input via the GPIO, and the output count is displayed on the on-board LEDs.
Equipment
-
Quartus II with ModelSIM and USB Blaster
-
DE0-Nano Development Board
-
USB Mini B Cable
2
Counter Design Using Schematic Entry
Sequential Logic on the Altera Cyclone IV FPGA
As the name implies, sequential circuits are circuits whose output follows a specific sequence. Counters are an example of a sequential circuit since the output changes sequentially with each clock pulse. In the previous
unit, combinational logic was defined as a digital system where the output depends on the particular combination applied to the input. The data flow was assumed to be in a forward direction through the system and there was nothing to impede the flow of data from I/P to O/P.
In the discussion of combinational logic, asynchronous counters were discussed, even though a counter is a sequential circuit rather than a combinational circuit. This seemed appropriate because the input to each flip flop is provided by the previous stage so the data flow was still in a forward direction. The circuit is actually only combinational immediately after a clock pulse. After the clock, the gates inside the latches allow the data
to propagate through to the output, but then the data is halted by the input to the next stage. Nothing happens in the circuit until the next clock pulse and then the data is latched into the next stage, and the process repeats. Circuits like this are sequential because the next state of the latch depends on the current state, giving rise to the sequence of outputs observed. We can thus define a sequential circuit as one which has
memory, such as a latch.
1. Asynchronous Sequential Logic
The asynchronous counter previously studied counts to a terminal state and then resets. Unfortunately, the decoder defining the modulus or terminal state of the counter generates a glitch at the terminal count which not only resets the counter, but allows the terminal count to proceed forward in the circuit during the time that
the counter is being reset. This terminal count state is a data corruption and destroys the operation of any devices following the counter. Synchronous Transition Asynchronous Transition
CLK A A
B
B
C D C
D 0 1 2 3 0 1 2 3 0 1 2 3
Glitch on line C
Corrupted Output cause next stage to crash.
Figure 1: Asynchronous Sequential Mod 4 Counter and Waveform Diagram
2. Synchronous Sequential Logic
Hazards such as oscillations and race conditions can take place when circuit operates asynchronously. In the circuit above, the reset line is actually a feedback line. A circuit that operates with feedback has the potential to oscillate. A new input changes the output which modifies the input etc. To fix this, the circuit must halt until the arrival of the next clock pulse, or is said to be synchronized with the clock. A circuit cannot simply decode an output state and reset asynchronously, but must wait for the clock to change state. This isn’t so in the circuit above. Since the terminal state doesn’t use a clock, it is asynchronous.
(LSB) CLK A
B C
3
2.1 Edge Triggering Since the synchronous circuit must change state in concert with the clock, transitions must occur only at the clock edge. Otherwise, the circuit is free to oscillate the whole time the clock is high. A circuit which is enabled during the active time of an input is level sensitive, while one which is enabled only when the input changes state is called edge sensitive. Synchronous circuits are usually positive edge sensitive, that is, they only change state at the rising edge of the clock.
2.2 Level Sensitive Gated D Latch
The SR latch formed by the last two NANDs below cannot change state unless the first pair of latches allows data through, or opens the gate. Note that the two inputs are combined into a single input called the Data or D input. This way the two inputs can never be the same and the undefined state of the SR latch is avoided. This is the simplest way to work with the latch since it only has one input. It is level sensitive since the output follows the input as long as the clock is high.
1
2
3
4
5
6
9
10
8
12
13
11
2
1
D Input
Clock
Q Out
/ Q Ouit
2.3 Master Slave Flip Flop
One way to make a flip flop appear edge sensitive is to use two latches with the same clock. The first latch is the master and the second is the slave. An inverter between the clock inputs ensures that they are never both active at the same time. 1
2
3
4
5
6
9
10
8
12
13
11
2
1
D Input
Clock
1
2
3
4
5
6
9
10
8
12
13
11
Q Out
/ Q Ouit
2
1
2
1
Master Latch
Slave Latch
Figure 2: Edge Sensitive D Flip Flop
Both latches are level sensitive, that is, the output for each follows the input as long as the clock is high. The inverter between the master clock input and the slave clock input causes the clocks to be out of synch.
Data is placed at the D input to the master and the clock is raised. At this time, the slave latch is disabled since
the clock is low, so the data can only be latched by the master.
When the clock is lowered, the master is disabled, and what ever data was on the data line when the clock was
lowered is latched by the master. At this time, the clock to the slave is now high, and the data held by the master is latched into the slave. Because the master is now disabled, the data is constant at the slave.
The leading inverter causes this Flip Flop to be rising edge triggered. What ever data is on the Data line at the rising edge of the clock is retained by the flip flop.
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2.4 State Diagram
Refer to the diagram of figure 1. The asynchronous counter cycles through states 0, 1, 2, 3, and then just gets into state 4 when it is reset, making it a mod four counter. The states are indicated by the count sequence shown along the bottom of the diagram. The mathematical model that describes it is called a machine or model, and each count represents a state the machine can assume.
This information is often shown as a STATE DIAGRAM as shown below. Not shown on this diagram is the temporary entry to state 4 which is immediately exited when the circuit is reset. The dotted arrow between each state is called a transition. Note that the state diagram has no timing information.
Transition
State
Figure 3: State Diagram with No Inputs
2.4 Timing Diagram
A waveform diagram showing the periods and time relationships between each of the circuit signals is referred to as a timing diagram. The timing diagram below shows a rising edge triggered mod 8 counter with a clock frequency of 100 MHz.
T clock
= 10 nS
CLK A
B
C
D 0 1 2 3 4 5 6 7 0 1 2 3
2.5 Setup and Hold Times
The setup time is the minimum time that the data must be held constant at the input before it can be clocked into the latches. The hold time is the minimum time that the data must be held constant after a clock edge is applied which will be latched onto by the internal latches.
Clock t setup
t hold
D input t pd
Q output
1
2
0
3
The maximum clock frequency is determined by the delay of the circuit. The flip flop has a propagation delay due to the gates forming the internal latches. The signal also encounters the inverters and other combinational logic, further delaying it. Finally, the signal must be present at the input of the latch a specified time to allow the latch feedback to latch onto the signal. The total propagation delay due to latches, feedback and setup is:
t Propagation Delay = t
Latch
+ t feedback
+ t
setup
Giving a maximum frequency of: F = 1/t pd
5
2.6 Direct Inputs
A sequential machine such as a counter may require external control lines. For example, an UP/DOWN counter may require a separate input line to cause the sequence to cycle up when high or cycle down when low. Direct inputs may also be added to pre-set or clear the machine manually. Notice that this will change the State Diagram shown in figure 3. Now each transition must show the state of the input to cause that transition, as well as the output when the machine is in each state. This is shown as Input/Output (I/O) for each transition.
2.7 State Machine
The edge sensitive D flip flop shown in figure 2 can be shown as a block with two inputs and one output. These can be shown together with the direct inputs and any combinational logic required to model the circuit diagram. A State Machine is a mathematical model that includes the State Diagram, Timing Diagram and Circuit Diagram. It will have several outputs depending on the states generated, and several inputs depending on the external control required. It will also include some combinational logic to generate the next state from the current state, or to determine the required sequence.
Direct Input X
LSB Flip Flop A Q
A
/Q
A
Q
B
/Q
B
Q
A
Q
B
/Q
A
/Q
B
Output
MSB
Flip Flop B
2.9
State Equations
Sometimes called excitation or characteristic or system equations, these are Boolean expressions describing the combinational logic between the flip flop input and the flip flop output. The flip flop output is the input to the equations and the D input is the output from the equations. In this case, they are:
D
A
= X Q
A
= /X • Q
A
+ X • /Q
A
D
B
= /X•Q
B
+
X•/Q
A
• Q
B +
X•Q
A
•/Q
B CLK Q / Q D
CLK Q / Q D
6
2.9 State Table
Is a table which shows the Current State, Input, Next State and Output. It is used to design the machine which means generating the decoding logic which yields the desired next state from the current state. In his case, the
output is not decoded from the sequence but is the /Q
B flip flop output..
The two state equations are used to determine the next state on the table based on the current state and the input. When the table is completed, the state diagram can be generated from the current and next states.
The table shows that when the input X is zero, the machine stays in its current state, but when X = 1, the machine transitions to the next state with each clock pulse. The input X behaves like a count enable. X = 0/1
X = 1/1
X = 1/1
X = 0/0
X = 0/1
X = 1/0
X = 1/0
X = 0/0
State Diagram for the State Table Above
01
10
00
11
Current State
Q
B
Q
A
Next State
Output
Input X = 0
Q
B
Q
A
Input X = 1
Q
B
Q
A
0 0
0 0
0 1
1
0 1
0 1
1 0
1
1 0
1 0
1 1
0
1 1
1 1
0 0
0
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Analysis Example 1
: Determine the state diagram for the synchronous sequential circuit below. Direct Input LSB Y
Flip Flop A Q
A
/Q
A
Q
B
/Q
B
Q
A
Q
B
/Q
A
/Q
B
Output
MSB
Flip Flop B
(a)
State Equations
D
A
= /Y + Q
A
D
B
= /Y•/Q
A
+
Y•/Q
B Out = Y•Q
B Current State
Q
B
Q
A
Next State
Output
Input Y = 0
Q
B
Q
A
Input Y = 1
Q
B
Q
A
Y= 1
Y = 0
0 0
1 1
1 0
0
0
0 1
0 1
1 1
0
0
1 0
1 1
0 0
1
0
1 1
0 1
0 1
1
0
(b) State Table
CLK Q / Q D
CLK Q / Q D
8
(c) State Diagram
Note from the following state diagram that this sequential machine has no exit from states 1 and 3 once it reaches that point. It probably initializes into the rest state 0, and then toggles between state 0 and 2 until initialization is complete. These two states could drive the Tx and Rx handshaking during a boot-
up sequence. Once the boot-up is complete, the sequence terminates initialization in state 3. After that it can only go between states 1 and 3 which could orchestrate a software reset during normal operation.
Y = 1/1
Y = 1/0
Y = 0/0
Y = 0/0
Y = 1/0 Y = 0/0
Y = 1/ 1 Y = 0/0
State Diagram for the State Table of Example 1
2.10 Analysis Summary
Example 1 demonstrates the steps involved in examining the operation of a sequential machine:
1.
Determine the state equations by inspection of the combinational logic feeding each D input.
2.
Determine the output equation by inspecting the decode logic feeding the output terminal.
3.
Use the state and output equations, to generate a state table. Note that every state must have an exit other than to itself so that the machine doesn’t hang if it accidentally ends up there.
4.
Complete a state diagram to graphically illustrate the operation determined by the state table.
Analysis Example 2
: Determine the state diagram for the synchronous sequential circuit below
where the LSB and MSB have been reversed between flip flop A and B. Input
/Q
A
/Q
B
Q
A
/Q
A
Q
B
/Q
B
Z Q
A
Q
B
Flip Flop A (MSB)
Output
10
00
11
01
CLK Q / Q
D CLK Q / Q
9
Flip Flop B (LSB)
3.0 Synchronous Sequential Design
The process of analyzing a synchronous sequential circuit follows the four step process outlined in step 2.10. More often, we need to design a circuit for use in a specific application. In the past, you may have simply used a 74160 or similar MSI IC to design a counter. This is a very limiting solution and inappropriate for most current applications for several reasons outlined here.
Recall from unit 1 that digital design today isn’t done with 7400 series TTL ICs that you have used in the lab. These are good to introduce students to digital circuits because they are simple, but they are obsolete as a technology in the field. The component density, power consumption, speed of execution, development time are all surpassed by VLSI technologies. When you design the latest video or network card, you will select an appropriate CPLD or FPGA. Into this IC
you will download -ALL- of your digital design. If you need a counter or a shift register, decoder, multiplexer,
all of these things will be designed on a computer and then downloaded to configure the uncommitted hardware on one of these ICs. Today, you must be able to design a counter rather than use an off the shelf solution because you will be required to place all of your logic onto a single IC.
Later in this course you will use a microcontroller and you will become familiar with the assembly code used to program it. These assembly instructions cause data to be transferred between registers while it is being operated on. The signals that cause the data to be shifted between registers as it is processed are generated by a state machine called a controller. Designing digital systems requires synchronous sequential design of the controller to manage arithmetic and transfer operations as well as bus arbitration.
It should be noted that it is possible and even desirable to use other flip flops than D type, but we use only D type here to keep the design straight forward. Students should be aware that using JK or T flip flops may result in a simpler circuit, but the design process will be more complex. The principles are the same however so that investigation is left to the student as individual study.
3.1 Design Steps
The design process is the reverse of the analysis process. To design a sequential circuit, the desired state diagram is generated from a statement of performance, and from that a state table is produced. The number of flip fops required is determined by the number of states required. The system equations are determined from the state table and simplified using Boolean reduction techniques. Finally, the circuit diagram is derived from the excitation equations.
3.2 Example:
Design a MOD 8 UP/DOWN counter.
This will require three flip flops since MOD 8 requires three bits (2
3 Bits = 8 States). Since
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it can be configured to count up or down, it will have one direct input. The outputs of each of the flip flops is the counter state so no output decoding is required. If other features were added, such as a count enable/disable line, preset or clear, these would all require additional input lines.
The state diagram following shows the eight states produced by a three bit counter with clockwise transitions to count up with input variable DIR =1, and counterclockwise transitions to count down when DIR = 0.
Step 1:
State Diagram
1
1
0
0
1
1
0
0
1
0
0
1
0 0
1
1
Step 2:
State Table
To complete the state
table, we need to place the next state
into each column for Y = 0 and
for Y = 1
in order to count up or
count down.
Step 3: State Equations
To derive the state equations, we could K-map the next state variable in terms of the current state and inputs. Software solutions will be required for more inputs because K-mapping doesn’t lend itself to Boolean 000
111
001
010
110
101
011
100
Current State
Q
C
Q
B
Q
A
Next State
Output
Input Y = 0
Q
C
Q
B
Q
A
Input Y = 1
Q
C
Q
B
Q
A
0 0 0
1 1 1
0 0 1
0 0 0
0 0 1
0 0 0
0 1 0
0 0 1
0 1 0
0 0 1
0 1 1
0 1 0
0 1 1
0 1 0
1 0 0
0 1 1
1 0 0
0 1 1
1 0 1
1 0 0
1 0 1
1 0 0
1 1 0
1 0 1
1 1 0
1 0 1
1 1 1
1 1 0
1 1 1
1 1 0
0 0 0
1 1 1
11
reduction beyond four variables. If a count enable was added to the design for example, each state would have
four arrows from it depending on the state of the inputs.
Q
A
Output: /Q
B
/Q
A
/Q
B
Q
A
Q
B
Q
A
Q
B
/Q
A
/Y/Q
C /Y Q
C Y Q
C Y/Q
C D
A
= /Q
A
Q
B
Output: /Q
B
/Q
A
/Q
B
Q
A
Q
B
Q
A
Q
B
/Q
A
/Y/Q
C /Y Q
C Y Q
C Y/Q
C D
B
= /Q
B
/Q
A
/Y + /Q
B
Q
A
Y + Q
B
Q
A
/Y + Q
B
/Q
A
Y Q
C
Output: /Q
B
/Q
A
/Q
B
Q
A
Q
B
Q
A
Q
B
/Q
A
/Y/Q
C /Y Q
C Y Q
C Y/Q
C D
C
= /Q
B
/Q
A
/Q
C
/Y + Q
C
/Q
B
Y + Q
C
Q
A
/Y + Q
B
/Q
A
Q
C + Q
B
Q
A /Q
C
Y
Step 3:
Circuit Diagram
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
1
0
1
0
0
1
0
12
3.3 Example:
Design a MOD 8 counter with ENABLE.
Step 1:
State Diagram
1
1
0
0 0
1
1
0 0
1
1
0 0 0
1
1
Step 2:
State Table
To complete the state table, we need to place the next state into each column for Y = 0 and for Y = 1
in order to count up or halt the count. Y is an ENABLE pin in this circuit.
000
001
111
110
010
101
011
100
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Step 3:
State Equations
Q
A
Output: /Q
B
/Q
A
/Q
B
Q
A
Q
B
Q
A
Q
B
/Q
A
/Y/Q
C /Y Q
C Y Q
C Y/Q
C D
A
=
Q
A
/Y + /Q
A
Y
= Q
A
Y
Q
B
Output: /Q
B
/Q
A
/Q
B
Q
A
Q
B
Q
A
Q
B
/Q
A
/Y/Q
C /Y Q
C Y Q
C Y/Q
C D
B
= /Y Q
B
+ Q
B
/Q
A
+ /Q
B
Q
A
Y = Q
B
(/Y + /Q
A
) + /Q
B
Q
A
Y __________
= Q
B
(Y Q
A
) + /Q
B
Q
A
Y = Q
A
Y Q
B
Q
C
Output: /Q
B
/Q
A
/Q
B
Q
A
Q
B
Q
A
Q
B
/Q
A
/Y/Q
C /Y Q
C Y Q
C Y/Q
C Current State
Q
C
Q
B
Q
A
Next State
Output
Input Y = 0
Q
C
Q
B
Q
A
Input Y = 1
Q
C
Q
B
Q
A
0 0 0
0 0 0
0 0 1
0 0 0
0 0 1
0 0 1
0 1 0
0 0 1
0 1 0
0 1 0
0 1 1
0 1 0
0 1 1
0 1 1
1 0 0
0 1 1
1 0 0
1 0 0
1 0 1
1 0 0
1 0 1
1 0 1
1 1 0
1 0 1
1 1 0
1 1 0
1 1 1
1 1 0
1 1 1
1 1 1
0 0 0
1 1 1
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
0
14
D
C
= /YQ
C
+ /Q
A
Q
C + /Q
B
Q
C
+ Q
B
Q
A
Y/Q
C
= (/Y + /Q
A
+ /Q
B
)
Q
C + Q
B
Q
A
Y/Q
C
________________
= (YQ
A
Q
B
)
Q
C + Q
B
Q
A
Y/Q
C
= Q
B
Q
A
Y Q
C
3.4 Note the pattern in Q
A
Q
B
Q
C
:
D
A
= Q
A
Y
D
B
= Q
B Q
A
Y
D
C
= Q
C Q
B
Q
A
Y
The counter can be implemented directly from the equations derived from the K-map, however re-expressing them as exclusive ORs leads to the simplification that any modulo counter can be built simply be XORing the previous stages ANDed together with the enable.
This is shown on the following diagrams. Either diagram will provide the same result, but the second one allows us to build any size counter without any further design effort. It is also a much cleaner design, however the XOR isn’t directly implemented on silicon so there is no savings in real estate or committed gates on and CPLD.
3.5 Note on Unused States:
Suppose you required a MOD 5 counter. This counter will have 5 states, 0 through 4, so it will require three bits. States 5, 6 and 7 of this counter will never be used, so they might not be shown in the state diagram. If the counter randomly came into one of those unused states however, the decode logic would then have no mechanism to return to a designed state, and the system would become unstable. To ensure that this never happens, all possible states must be shown on the state diagram, and if they are unused states, simply lead into state 0 for all inputs.
15
Fig. A: Direct Implementation of MOD 8 Counter
Fig. B: Scalable Implementation of MOD 8 Counter
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4.1
Laboratory Activity
In this activity, you will implement the MOD 8 counter with Up/Down control, examined in step 3.1. In that example, the counter counts up from 000 to 111 and repeats while the mode control input is high. When the mode control is low, the counter counts backwards from 111 to 000 and repeats. This is a synchronous design so the count changes state only on the rising edge of the clock input.
4.1 Input Connections
We require two input signals for this counter. We need a single line input to direct the count sequence, and a clock signal to cause the machine to transition between states. It is convenient to use a wire connected high or
low to one of the GPIO inputs and the count direction or mode control. We’ll use a wire connected to an I/P and move the other end between logic high and low on the GPIO header. The clock can be obtained by the on-board switches since they are debounced.
Mode Control:
FPGA Input Pin GPIO0 HEADER PIN
PIN_E10
27
34 Clock: PIN_J15
On-board pushbutton switch KEY0.
4.2 Output Connections
We require three outputs to indicate the count state. We can use the on-board LEDs to display the state.
Label these as shown:
FPGA Output Pin
Output Bit On Board LED PIN_A15 A
0
PIN_A13 B
1 PIN_B13 C
2 You may have to add Output buffers to the three output pins to drive the LEDs. See the schematic following.
5.0 Quartus Schematic Entry
Pin 34 can be connected to pin11 for a high input or to pin 12 for a low input.
Mode Control I/P connected to pin 34.
17
Following the example of the previous laboratory activity, the schematic diagrams can now be entered into the
Quartus IDE and loaded onto the FPGA. Launch the Quartus IDE and create a new project called Counter and
enter the schematic of step 3.1. Save your project.
5.1 Compile the Counter Schematic
Run the compiler and correct any mistakes. Re-compile until it compiles successfully. The Quartus II IDE displays messages produced during compilation in the Messages window. If the block diagram design file is correct, one of the messages will state that the compilation was successful with no errors. If the Compiler does not report zero errors, then there is at least one mistake in the schematic entry. In this case a message corresponding to each error found will be displayed in the Messages window. Double-clicking
on an error message will highlight the offending part of the circuit in the Graphic Editor window. 5.2 Pin Assignment
Run the Assignment Editor
and label the input and output pins as defined in section 1.0 and 1.1.
To save the assignments made, choose File > Save
. You can also simply close the Assignment Editor window,
in which case a pop-up box will ask if you want to save the changes to assignments; click Yes. Recompile the circuit, so that it will be compiled with the correct pin assignments. This may take some time, the message window will indicate NETLIST successful
if your pins have been assigned.
Note Output Buffers …
18
6.0 Simulating the Designed Circuit
Open the Waveform Editor window by selecting File > New from the top menu. That gives the window shown following on the left. Choose University Program VWF
(Vector Waveform File) and click OK
. That will open the Waveform Editor window.
In the editor window, set the desired simulation to run from 0 to 100 μs by selecting Edit > Set End Time
. Enter 100 μs in the dialog box below an OK
. Selecting View > Fit in Window
displays the entire simulation range in the window. Resize the window to its maximum size from the upper right corner control.
6.1 Functional Simulation
To perform the functional simulation, return to the top menu of the Simulation Waveform Editor and select Simulation
> RUN FUNCTIONAL SIMULATION.
Wait a moment for the simulation screen to display. Add the clock, Mode and Output signals to the simulation. Click on the Clock name to highlight it and then click OVERWRITE CLOCK
from the top menu. In the pop-up, select 10μSec
. for the period, and
OK
.
6.2 Simulation Verification
With the mode control low, the simulation counts down and repeats as shown below.
With the mode control high, the simulation counts up and repeats as shown below.
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19
7.0 Programming and Configuring the FPGA The FPGA device must be programmed and configured to implement the designed circuit. We will use
JTAG mode, so the configuration data is loaded directly into the FPGA device. Remember that if the FPGA is configured in this manner, it will retain its configuration as long as the power remains turned on. The configuration information is lost when the power is turned off. Select Tools > Programmer
and the counter.sof if it is visible.
If the configuration file counter.sof is listed not in the window above, click Add File
and select it from the C\altera_lite\16.0\output folder. This is a binary file produced by the Compiler’s Assembler, containing data needed to configure the FPGA device. Click on the Program/Configure
check box.
Click on AUTO DETECT
in the programmer window (and wait), and then press Start
in the programmer window. The progress bar in the programming window will be green at 100% and say SUCCESSFUL
when the configuration data has been downloaded successfully. If you see an error reported by Quartus II software indicating that programming failed, check to ensure that the board is properly powered on.
8.0 Testing the Designed Circuit
Since the JTAG programmer was used, you must not
unplug your Nano or you will lose your programming. The JTAG programmer places code in SRAM and is erased on power down.
Press the on-board pushbutton KEY0 and observe the LEDs. They should transition between count states depending on the status of the GPIO mode control. The count should increment with each key press while the mode control is high, and decrement with each keypress while the mode control is low.
When you power down the DE0-Nano, the program will disappear from the on-board memory. When you power back up, the Celon Eyes will exercise the LED bank once again.
9.0 Individual Assignment
When you have demonstrated your functioning Mod 8 Up/Down counter to your instructor, you will be assigned a new counter to design. Follow the examples in the pre-lab tutorial to add another output pin to your
counter, or to add an enable pin. You will require a state table and state diagram to design your Mod 16 or enabled counter. Be prepared to generate new state equations and create a new schematic to complete the individual assignment.
Example:
Design a Mod16 Down Counter with a Count Enable input, which steps over all even numbered states (ie: only transitions between odd states in descending sequence). Demonstrate this to your instructor.
Your design must include: 1. State Diagram
2. State Table
3. State Equations
4. Circuit Diagram
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Recommended textbooks for you
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