homework 2 (1)

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Electrical Engineering

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Feb 20, 2024

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EEE 425/591 Digital Systems and Circuits Spring 2024 Homework #2 (100 points) Due Thursday, February 9 th , 11:59pm. 1. Inverter VTC and Noise Margin (25 points) Given an CMOS inverter, answer the following questions using Figure 1. a) (5 points) Derive the analytic expressive of the CMOS inverter VTC, i.e., 𝑉 ??? as a function of 𝑉 ?? for region 2. Assume | 𝑉 ?? | = 𝑉 ?? and ? p = ? n . b) (10 points) Calculate the noise margins, NM L and NM H for an inverter operating at 𝑉 ?? = 1.5 𝑉 with | 𝑉 ?? | = 𝑉 ?? = 0.5 𝑉 . c) (10 points) If PMOS is biased to 0V, i.e., 𝑉 𝑔? , ? = − 𝑉 ?? , does the VTC of this inverter shift right or left? Justify your answer. Figure 1. Voltage Transfer Curve (VTC) of a CMOS inverter For Question 2-3, use the values in Table 1. Table 1. Transistor parameters NMOS PMOS μ n = 560 cm 2 /Vs W n = 0.5 μm μ p = 220 cm 2 /Vs W p = 1.0 μm L n,source = 0.70 μm L n,drain = 0.70 μm L p,source = 0.70 μm L p,drain = 0.70 μm L n,gate = 0.25 μm V Tn = 0.6 V L p,gate = 0.25 μm V Tp = -0.6 V ? ? 0 = 1.7 fF/um 2 ? ??? 0 = 0.4 fF/um ? ? 0 = 1.8 fF/um 2 ? ??? 0 = 0.36 fF/um Both NMOS and PMOS ? 𝑔? 0 = 0.3 fF/um ? 𝑔𝑑 0 = 0.3 fF/um ? ?? = 4 fF/um 2 |φ 0 | = 1 V m = 1/2 (bottom plate) m = 1/3 (sidewall cap) V DD = 2.5 V

2. Static Inverter Analysis (30 points) For an inverter with PMOS and NMOS device with properties from Table 1, answer the questions. a) (5 points) Find the switching voltage V M b) (10 points) Calculate the values of R n and R p c) (5 points) We would now like to construct an inverter whose switching voltage is exactly half of the supply voltage. How would you size the transistors? d) (10 points) The inverter drives a load of 74fF. Calculate t pHL and t pLH . (Note: do not ignore the transistor capacitances) 3. CMOS Capacitance (25 points) Consider a CMOS inverter whose input is at 2.0V and output at 0V. Refer to the NMOS and PMOS device parameters from Table 1. For both devices, specify their working regions and calculate the below list of capacitances. a) (5 points) ? 𝑔? b) (5 points) ? 𝑔𝑑 c) (5 points) ? 𝑑𝑏 d) (5 points) ? s 𝑏 e) (5 points) ? 𝑔𝑏 4. CMOS INV Power (20 points) Assume a 100 ?? 2 chip working at 1 GHz and 𝑉 ?? = 1 𝑉 , with an average activity factor of 𝛼 = 0.1. It uses a standard cell process with an average switching capacitance of 500 ?𝐹 / ?? 2 . a) (5 points) Estimate the dynamic switching power of this chip. b) (5 points) If the total sub-threshold current is 100 mA, estimate the power density of the chip. c) (10 points) If you would like to scale down 𝑉 ?? to save power and reduce 𝑉 ? to maintain performance, use equation to explain how the dynamic power and static power will change, respectively (go up or down and why).

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