homework 2 solution

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Feb 20, 2024

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EEE 425/591 Digital Systems and Circuits Spring 2024 Homework #2 (100 points) Due Thursday, February 9 th , 11:59pm. 1. Inverter VTC and Noise Margin (25 points) Given an CMOS inverter, answer the following questions using Figure 1. Figure 1. Voltage Transfer Curve (VTC) of a CMOS inverter a) (5 points) Derive the analytic expressive of the CMOS inverter VTC, i.e., ? ??? as a function of ? ?? for region 2. Assume | ? ?? | = ? ?? and ? p = ? n . NMOS is in saturation and PMOS is in linear region. 1. Applying KCL to inverter logic, 𝐼 ?? = 𝐼 ?? 1 2 ? ? ′ ( ? 𝐿 )(? ?? − ? ?? ) 2 = ? ? ′ ( ? 𝐿 )[(? ?? − |? ?? |)? ?? − 1 2 ? ?? 2 ] We will cancel out ? = ? ′ ( ? ? ) values and use ? ? = ? ?? = |? ?? | 1 2 (? ? − ? ? ) 2 = [(? ?? − ? ? − ? ? )(? ?? − ? ? ) − 1 2 (? ?? − ? ? ) 2 ] = ? ?? 2 − ? ?? ? ? − ? ? ? ?? + ? ? ? ? − ? ? ? ?? + ? ? ? ? − 1 2 (? ?? − ? ? ) 2 2. To solve for 2 variables, we will use ?? 𝑜 ?? 𝑖 = −1 from the definition of these points. Let’s compute partial derivative equation of 1. (? ? − ? ? )?? ? = −? ?? ?? ? − ? ?? ?? ? + ? ? ?? ? + ? ? ?? ? + ? ? ?? ? + (? ?? − ? ? )?? ? (? ? − ? ? + ? ?? − ? ? )?? ? = (−? ?? + ? ? + ? ? + ? ?? − ? ? )?? ? ? ? − ? ? + ? ?? − ? ? = −? ? − ? ? + ? ? 2? ? = 2? ? + ? ?? 𝒗 ? = 𝒗 𝒊 + ? 𝑫𝑫 ?

b) (10 points) Calculate the noise margins, NM L and NM H for an inverter operating at ? ?? = 1.5 ? with | ? ?? | = ? ?? = 0.5 ? . First, plug in the given values to the part a) equation. ? ? = ? ? + ? ?? 2 = ? ? + 0.75 Now, we will substitute above equation to eq 1 from part a). 1 2 (? ? − 0.5) 2 = (1.5 − ? ? − 0.5)(1.5 − ? ? − 0.75) − 1 2 (1.5 − ? ? − 0.75) 2 = (1 − ? ? )(0.75 − ? ? ) − 1 2 (0.75 − ? ? ) 2 = (0.75 − ? ? )[(1 − ? ? ) − 0.5(0.75 − ? ? )] = (0.75 − ? ? )(0.625 − 0.5? ? ) 0.5? ? 2 − 0.5? ? + 0.125 = 0.46875 − ? ? + 0.5? ? 2 𝒗 𝒊 = 𝒗 𝒊? = ?. ????? We will plug back to the first equation for output voltage. 𝒗 ? = 𝒗 ?? = 𝒗 𝒊 + ?. ?? = ?. ????? For region 4, we will repeat the same procedure to compute v iH , v oL . 1. 𝐼 ??,?????? = 𝐼 ??,?????????? 1 2 ? ? (? ?? − |? ?? |) 2 = ? ? [(? ?? − ? ?? )? ?? − 1 2 ? ?? 2 ] (? ?? − ? ? − |? ?? |) 2 = 2(? ? − ? ?? )? ? − ? ? 2 (1.5 − ? ? − 0.5) 2 = 2(? ? − 0.5)? ? − ? ? 2 2. Slope = -1 −2(1 − ? ? )?? ? = 2? ? ?? ? + ?? ? (2? ? − 1) − 2? ? ?? ? Divide both sides by dv i and plug in dv o /dv i = -1. 2? ? − 2 = 2? ? − (2? ? − 1) + 2? ? 4? ? = 4? ? − 1 ? ? = ? ? − 0.75 Substituting equation 2 to 1, (1 − ? ? ) 2 = 2(? ? − 0.5)(? ? − 0.75) − (? ? − 0.75) 2 = (? ? − 0.75)(2? ? − 1 − ? ? + 0.75) = (? ? − 0.75)(? ? − 0.25) 1 − 2? ? + ? ? 2 = ? ? 2 − ? ? + 0.1875 𝒗 𝒊 = 𝒗 𝒊? = ?. ????? Now, we plug back to equation 2 𝒗 ? = 𝒗 ?? = ?. ???? − ?. ?? = ?. ????? Finally, we will compute each noise margins. ?? ? = 𝒗 ?? − 𝒗 ?? = ?. ???? − ?. ???? = ?. ???? ?? ? = 𝒗 ?? − 𝒗 ?? = ?. ???? − ?. ???? = ?. ????

c) (10 points) If PMOS is biased to 0V, i.e., ? ?? , ? = − ? ?? , does the VTC of this inverter shift right or left? Justify your answer. If PMOS is biased to 0V, i.e., V sg =V DD , PMOS is turned on, providing a path to V DD . As a result, NMOS requires a higher input voltage in order to overcome PMOS and enter the saturation region. So, the VTC shifts to the right. For Question 2-3, use the values in Table 1. Table 1. Transistor parameters NMOS PMOS μ n = 560 cm 2 /Vs W n = 0.5 μm μ p = 220 cm 2 /Vs W p = 1.0 μm L n,source = 0.70 μm L n,drain = 0.70 μm L p,source = 0.70 μm L p,drain = 0.70 μm L n,gate = 0.25 μm V Tn = 0.6 V L p,gate = 0.25 μm V Tp = -0.6 V ? ? 0 = 1.7 fF/um 2 ? ??? 0 = 0.4 fF/um ? ? 0 = 1.8 fF/um 2 ? ??? 0 = 0.36 fF/um Both NMOS and PMOS ? ?? 0 = 0.3 fF/um ? ?? 0 = 0.3 fF/um ? ?? = 4 fF/um 2 |φ 0 | = 1 V m = 1/2 (bottom plate) m = 1/3 (sidewall cap) V DD = 2.5 V Formulas Propagation delay t p = 0.7RC Transistor resistance 𝑅 ≅ 1 ? ′ ? 𝐿 (? ?? − ? ?ℎ ) Region C GB C GS C GD Cutoff C ox WL C 0 W C 0 W Linear 0 C ox WL/2+ C 0 W C ox WL/2+ C 0 W Saturation 0 (2/3) C ox WL+ C 0 W C 0 W

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2. Static Inverter Analysis (30 points) For an inverter with PMOS and NMOS device with properties from Table 1, answer the questions. a) (5 points) Find the switching voltage V M ? = √ 𝜇 ? ? ? 𝜇 ? ? ? = √ 220 ∗ 1 ∗ 10 −6 560 ∗ 0.5 ∗ 10 −6 = 0.886 ? ? = ? ?? + ?(? ?? − |? ?? |) 1 + ? = 0.6 + 0.886(2.5 − | − 0.6|) 1 + 0.886 = ?. ????? b) (10 points) Calculate the values of R n and R p 𝑅 ? ≅ 1 ? ? ′ ? 𝐿 (? ?? − ? ?ℎ ) = 1 𝜇 ? ? ?? ? 𝐿 (? ?? − ? ?ℎ ) = 1 560 ∗ 10 −4 ? 2 ?? ∗ 4 ∗ 10 −15 𝐹 𝜇? 2 ∗ 10 12 𝜇? 2 1? 2 ∗ 0.5 0.25 ∗ (2.5 − 0.6) = ?. ???𝒌𝛀 𝑅 ? ≅ 1 ? ? ′ ? 𝐿 (? ?? − ? ?ℎ ) = 1 𝜇 ? ? ?? ? 𝐿 (? ?? − ? ?ℎ ) = 1 220 ∗ 10 −4 ? 2 ?? ∗ 4 ∗ 10 −15 𝐹 𝜇? 2 ∗ 10 12 𝜇? 2 1? 2 ∗ 1 0.25 ∗ (2.5 − 0.6) = ?. ???𝒌𝛀 c) (5 points) We would now like to construct an inverter whose switching voltage is exactly half of the supply voltage. How would you size the transistors? ? ? = ? ?? + ?(? ?? − |? ?? |) 1 + ? = 1.25? 1.25 + 1.25? = 0.6 + ?(2.5 − 0.6) 0.65 = 1.9? − 1.25? = 0.65? ? = 1 = √ 220?? 2 /?? ∗ ? ? 560?? 2 /?? ∗ ? ? If we set the NMOS transistor size as is, then PMOS transistor would be resized as below. ? ? = 0.5𝜇? ∗ 56 22 = ?. ???𝝁𝒎 d) (10 points) The inverter drives a load of 74fF. Calculate t pHL and t pLH . (Note: do not ignore the transistor capacitances) First, we need to compute transistor capacitances to find the total capacitance. ? ??? = ? ? ?𝐿 ? (1 + ? ?? 𝜙 0 ) ?? + ? ??? (2𝐿 ? + ?) (1 + ? ?? 𝜙 0 ) ???? = 1.7?𝐹 𝜇? 2 ∗ 0.5𝜇? ∗ 0.7𝜇? (1 + 1.25 1 ) 1 2 + 0.4?𝐹 𝜇? 2 (2 ∗ 0.7𝜇? + 0.5𝜇?) (1 + 1.25 1 ) 1 3 = 0.3966 + 0.5799 = 0.9765?𝐹 ≈ ?. ??𝒇𝑭

? ??? = 1.8?𝐹 𝜇? 2 ∗ 1𝜇? ∗ 0.7𝜇? 2.25 1 2 + 0.36?𝐹 𝜇? 2 (2 ∗ 0.7𝜇? + 1𝜇?) 2.25 1 3 = 0.84 + 0.6596 = 1.4996?𝐹 ≈ ?. ?𝒇𝑭 ? ??? + ? ??? = (? ? + ? ? )? ??0 = (1 + 0.5)0.3 ∗ 10 −15 = ?. ??𝒇𝑭 ? ??? = ? ??? + ? ??? + 2(? ??? + ? ??? ) + ? ? = 1.5?𝐹 + 0.98?𝐹 + 2(0.45?𝐹) + 74?𝐹 = ??. ??𝒇𝑭 Now we combine with resistances from part b) to compute propagation delay. ? ??? = 0.69𝑅 ? ? = 0.69 ∗ 1.174?Ω ∗ 77.38?𝐹 = ??. ????𝒔 ? ??? = 0.69𝑅 ? ? = 0.69 ∗ 1.495?Ω ∗ 77.38?𝐹 = ??. ????𝒔 3. CMOS Capacitance (25 points) Consider a CMOS inverter whose input is at 2.0V and output at 0V. Refer to the NMOS and PMOS device parameters from Table 1. For both devices, specify their working regions and calculate the below list of capacitances. NMOS: linear region because ? ?? = 0 < ? ?? − ? ?ℎ = 2 − 0.6 = 1.4 , ? ?? = 2 > ? ?ℎ = 0.6 PMOS: cutoff region because ? ?? = 2.5 − 2 = 0.5 < |? ?ℎ | = 0.6 a) (5 points) ? ?? ? ??? = ? ?? ?𝐿 2 + ? ? ? = 4?𝐹 𝜇? 2 0.5𝜇? ∗ 0.25𝜇? 2 + 0.3?𝐹 𝜇? ∗ 0.5𝜇? = ?. ?𝒇𝑭 ? ??? = ? ? ? = 0.3?𝐹 𝜇? ∗ 1𝜇? = ?. ?𝒇𝑭 b) (5 points) ? ?? The values will be same as C gs from part a). ? ??? = ?. ?𝒇𝑭, ? ??? = ?. ?𝒇𝑭 c) (5 points) ? ?? ? ??? = ? ? ?𝐿 ? (1 + ? ?? 𝜙 0 ) ?? + ? ??? (2𝐿 ? + ?) (1 + ? ?? 𝜙 0 ) ???? = 1.7?𝐹 𝜇? 2 ∗ 0.5𝜇? ∗ 0.7𝜇? (1 + (0 − 0) 1 ) 1 2 + 0.4?𝐹 𝜇? 2 (2 ∗ 0.7𝜇? + 0.5𝜇?) (1 + (0 − 0) 1 ) 1 3 = 0.595 + 0.76 = ?. ???𝒇𝑭 ? ??? = 1.8?𝐹 𝜇? 2 ∗ 1𝜇? ∗ 0.7𝜇? (1 + 2.5 1 ) 1 2 + 0.36?𝐹 𝜇? 2 (2 ∗ 0.7𝜇? + 1𝜇?) (1 + 2.5 1 ) 1 3 = 0.6734 + 0.569 = ?. ????𝒇𝑭

d) (5 points) ? s ? ? ??? = ? ? ?𝐿 ? (1 + ? ?? 𝜙 0 ) ?? + ? ??? (2𝐿 ? + ?) (1 + ? ?? 𝜙 0 ) ???? = ? ??? = ?. ???𝒇𝑭 ? ??? = 1.8?𝐹 𝜇? 2 ∗ 1𝜇? ∗ 0.7𝜇? 1 1 2 + 0.36?𝐹 𝜇? 2 (2 ∗ 0.7𝜇? + 1𝜇?) 1 1 3 = 1.26 + 0.864 = ?. ??𝒇𝑭 e) (5 points) ? ?? ? ??? = ?𝑭 ? ??? = ? ?? ?𝐿 = 4? 𝜇? 2 ∗ 1𝜇? ∗ 0.25𝜇? = ?𝒇𝑭 4. CMOS INV Power (20 points) Assume a 100 ?? 2 chip working at 1 GHz and ? ?? = 1 ? , with an average activity factor of 𝛼 = 0.1. It uses a standard cell process with an average switching capacitance of 500 ?𝐹 / ?? 2 . a) (5 points) Estimate the dynamic switching power of this chip. 𝑃 ? = 𝑃 ??? = 𝛼? ? ? ?? 2 ? = 0.1 ∗ 500?𝐹 ?? 2 ∗ 100?? 2 ∗ 1? 2 ∗ 10 9 = ?? b) (5 points) If the total sub-threshold current is 100 mA, estimate the power density of the chip. 𝑃 ????? = 𝑃 ??? + 𝑃 ?????? = 5 + 𝐼 ??? ? ?? = 5 + 0.1𝐴 ∗ 1? = ?. ?? 𝑃???? ??????? = 𝑃 ????? 𝐴??? = 5.1? 100?? 2 = 0.051?/?? 2 = ??𝒌?/𝒎 ? c) (10 points) If you would like to scale down ? ?? to save power and reduce ? ? to maintain performance, use equation to explain how the dynamic power and static power will change, respectively (go up or down and why). 𝑃 ??? = 𝛼?? ?? 2 ? shows that P is quadratically proportional to V DD . Hence, V DD ↓ , P dyn ↓ . To maintain the performance: ? ? ∝ (? ? + ? 𝐿 ? ) ?? 𝐷𝐷 (? 𝐷𝐷 −? 𝑡ℎ ) 2 When you scale down ? ?? by ? 1 , you have to scale down ? th by ? 2 to satisfy ? ?? ? 1 ( ? ?? ? 1 − ? ?ℎ ? 2 ) 2 = ? ?? (? ?? − ? ?ℎ ) 2 ? 2 = √ ? 1 ? ?ℎ ? ?ℎ − (1 − 1 √ ? 1 )? ?? For static power, it will change as 𝑃 ?????? = 𝐼 ??? ? ?? ∝ ? ? 𝑡ℎ − ??? ? ? ??

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= ? ? 𝑡ℎ ? 2 − ??? ? ? ?? ? 1 = ? ? 𝑡ℎ −(1− 1 ? 1 )? 𝐷𝐷 √ ? 1 − ??? ? ? ?? ? 1 Assume ??? ? = 75?? and ? ?ℎ < 1? (?. ?. 0.3?) . Then, static power will increase when s 1 >1. An intuitive explanation: As ? ?? ↓, 𝐼 ??? will exponentially increase when ? ? ↓. Then 𝑃 ?????? ↑.