Midterm HW

Find static DC current

8.

demonstrate how the AND, OR, Inverter, and NAND Integrated Circuits work.   Using NI Multisim, design four different circuits: AND, OR, Inverter, and NAND On the one working space, place the four circuits, each taking up a quadrant of space with labels:   AND           OR   Inverter      NAND       Each Circuit should include: Power: VCC and DGND A switch or two switches for input: SPDT All switches should use the same keys to activate: A and B, or just A for the Inverter. A resistor and LED for output--your color choice(s) The appropriate 74LS...  IC chip. Label the chip function: Example AND Gates Wiring that uses the correct color coding for this class. Black - Ground Red - Power/VCC Blue - Input from Switches Green - Output Yellow - Connect two logic gates White - Miscellaneous

A single-phase half-bridge inverter has load R =2Ω and dc source voltage Vs/2 =115V. (a) Sketch the waveforms for Vo , load current i01 currents through thyristor 1 and diode1and voltage across thyristor TI. Harmonics other than fundamental component are neglected.Indicate the devices that conduct during different intervals of one cycle.(b) Find the power delivered to load due to fundamental current.(c) Calculate THD and HF.

The transistor inverter circuit shown in the figure is desired to be designed so that the Ic saturation current is 8mA. Find the Rb and Rc resistances so that the IB current is 120% of the max IB current. (Note: Max IB current is at saturation Ic.)

2. Show how the output conductance of a transistor affects the voltage transfer characteristics (butterfly curve) of a cross-coupled inverter cell? (output resistance/conductance defined in the image below). on-resistance output resistance on-current -1,(Ves = Vps = Vpp) RON I ps transconductance (mA/um) 8m AVas lWas GS V ps VDD Assume symmetric N- and P-MOS devices.

Write true or false for each statement 1) Phosphorous ions are implanted into active areas of NMOS transistors. 2) P-well is required for PMOS transistors if lightly doped p-type silicon wafer is used as a substrate. 3) Silicon dioxide is a very good conductor like metal 1 layer. 4) Aluminum is used for making a gate terminal on top of a SiO2 layer in CMOS fabrication. 5) Photolithography is a process of implanting atoms into the silicon substrate to make transistors.

2. a) With reference to the output characteristics explain what is meant by the terms cutoff, active and saturation of a bipolar junction transistor. Indicate these regions on a sketch of the transistor output characteristic. b) What is the equation of the load line shown in Figure 2b? Rc + 12 volts Rg +V8 Figure 2b Question 2 continues on next page

P-channel MOSFET with heavily doped P-type poly-Si gate has a threshold voltage of -I. S Y with V sb = 0 V. When a 5 V reverse bias is applied to the substrate. the threshold voltage changes to 2.3 V. (a) What is the dopant concentration in the substrate if the oxide thickness is 100 nm? (b) What is the threshold voltage if Vsb is 2.5 V?  

a) Design a saturated load inverter shown in the figure below with VDD = 3.3 V and VL = 0.25 V. Assume Ipp = 30 µA, K’n = 25 µA/V²' and VIN = 0.65 V. Verify your design using PSPICE or Multisim package. b) Find the noise margins (NML and NMH) associated with the designed inverter graphically and compare them with your calculation. VDD ML HE VSB Ms

The following question is related to isolated de to de converters.(a)Discuss the requirements for electrical isolation in relation to do to deconverters.

(b) List the steps needed to test any four-terminal MOSFET with the same setup to determine which terminal is the gate, which terminal is the body, whether the device is a N-cha (c) If the gate oxide were destroyed by a static electricity discharge, speculate on how the current readings might be different from those that were observed.Be detailed in your response.

The NMOS and PMOS transistors have the following characteristics. The channel length is 350 nanometers. For NMOS: tox=50nm, Vtn-0.25V, un-560cm²/vsec, W=700nm, L=350nm For PMOS: tox-50nm, Vtp=-0.35V, up-240cm²/vsec, W=700nm, L=350nm a) Compute the NMOS gate capacitance CG in Femto Farads. b) Compute the resistance Rp for PMOS if the power supply voltage (Vdd) is 3.3 volts and the threshold voltage is 0.35 volts. Use the multiplying adjustment factor as 2.5.