Processing stages: The processing of an instruction has number of operations. The operations are organized into particular sequence of stages. It attempts to follow a uniform sequence for all instructions. The description of stages are shown below: Fetch: It uses program counter “PC” as memory address to read instruction bytes from memory. The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction. It fetches “valC” that denotes an 8-byte constant. It computes “valP” that denotes value of “PC” plus length of fetched instruction. Decode: The register file is been read with two operands. It gives values “valA” and “valB” for operands. It reads registers with instruction fields “rA” and “rB”. Execute: In this stage the ALU either performs required operation or increments and decrements stack pointer. The resulting value is termed as “valE”. The condition codes are evaluated and destination register is updated based on condition. It determines whether branch should be taken or not in a jump instruction. Memory: The data is been written to memory or read from memory in this stage. The value that is read is determined as “valM”. Write back: The results are been written to register file. It can write up to 2 results. PC update: The program counter “PC” denotes memory address to read bytes of instruction from memory. It is used to set next instruction’s address. Backward taken, forward not taken (BTFNT): It predicts that if branches to lower addresses the next instruction will be taken. If it branches to higher addresses then next instruction will not be taken. This strategy has a success rate of 65%. The loops are executed multiple times and are closed by backward branches. The forward branches are used for conditional operations, and are less likely to be taken.

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Chapter 4.5, Problem 4.43PP

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to 2 results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Backward taken, forward not taken (BTFNT):

It predicts that if branches to lower addresses the next instruction will be taken.

If it branches to higher addresses then next instruction will not be taken.

This strategy has a success rate of 65%.

The loops are executed multiple times and are closed by backward branches.

The forward branches are used for conditional operations, and are less likely to be taken.

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