Computer Science: An Overview (12th Edition)
12th Edition
ISBN: 9780133760064
Author: Glenn Brookshear, Dennis Brylow
Publisher: PEARSON
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Chapter 2, Problem 55CRP
Program Plan Intro
Increase in the speed of execution does not increase the performance of the computer. To increase the performance of the computer there is a need to improve the machine’s throughput, which means the total amount of work done in a given amount of time.
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A measure of system throughput that relies only on MIPS or FLOPS has what?
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**course of study: Computer Architecture
Chapter 2 Solutions
Computer Science: An Overview (12th Edition)
Ch. 2.1 - What sequence of events do you think would be...Ch. 2.1 - What information must the CPU supply to the main...Ch. 2.1 - Prob. 3QECh. 2.2 - Prob. 1QECh. 2.2 - In the text, JUMP instructions were expressed by...Ch. 2.2 - Is the instruction If 0 equals 0, then jump to...Ch. 2.2 - Write the example program in Figure 2.7 in actual...Ch. 2.2 - The following are instructions written in Vole...Ch. 2.2 - What is the difference between the instructions...Ch. 2.2 - Here are some instructions in English. Translate...
Ch. 2.3 - Prob. 1QECh. 2.3 - Suppose the Vole memory cells at addresses 0xB0 to...Ch. 2.3 - Suppose the Vole memory cells at addresses 0xA4 to...Ch. 2.3 - Suppose the Vole memory cells at addresses 0xF0 to...Ch. 2.4 - Prob. 1QECh. 2.4 - Prob. 2QECh. 2.4 - Prob. 3QECh. 2.4 - a. Suppose you XOR the first 2 bits of a string of...Ch. 2.4 - Prob. 5QECh. 2.4 - Prob. 6QECh. 2.4 - Prob. 7QECh. 2.4 - Prob. 8QECh. 2.4 - Prob. 9QECh. 2.4 - Prob. 10QECh. 2.4 - Using Vole machine language (Appendix C), write a...Ch. 2.4 - Prob. 12QECh. 2.5 - Prob. 1QECh. 2.5 - Prob. 2QECh. 2.5 - Prob. 3QECh. 2.6 - The hypotenuse example script truncates the sides...Ch. 2.6 - Prob. 2QECh. 2.6 - The Python built-in function str () will convert a...Ch. 2.6 - Use the Python built-in bin () to write a script...Ch. 2.6 - Prob. 6QECh. 2.7 - Referring back to Questions 3 of Section 2.3, if...Ch. 2.7 - Prob. 2QECh. 2.7 - Suppose there were two central processing units...Ch. 2 - a. In what way are general-purpose registers and...Ch. 2 - Answer the following questions in Vole machine...Ch. 2 - Prob. 3CRPCh. 2 - What is the value of the program counter in the...Ch. 2 - Prob. 5CRPCh. 2 - Prob. 6CRPCh. 2 - Prob. 7CRPCh. 2 - Suppose a machine language is designed with an...Ch. 2 - Translate the following instructions from English...Ch. 2 - Rewrite the program in Figure 2.7 assuming that...Ch. 2 - 11. Classify each of the following instructions...Ch. 2 - Prob. 12CRPCh. 2 - Prob. 13CRPCh. 2 - Suppose the memory cells at addresses 0x00 through...Ch. 2 - Suppose the memory cells at addresses 0x00 through...Ch. 2 - Suppose the memory cells at addresses 0x00 through...Ch. 2 - Suppose the memory cells at addresses 0x00 through...Ch. 2 - Prob. 18CRPCh. 2 - If the Vole executes an instruction every...Ch. 2 - Prob. 20CRPCh. 2 - Prob. 21CRPCh. 2 - Prob. 22CRPCh. 2 - Prob. 23CRPCh. 2 - Write a program in Vole to compute the sum of...Ch. 2 - Prob. 26CRPCh. 2 - Prob. 27CRPCh. 2 - Suppose the following program, written in Vole, is...Ch. 2 - Summarize the steps involved when the Vole...Ch. 2 - Summarize the steps involved when the Vole...Ch. 2 - Summarize the steps involved when the Vole...Ch. 2 - Suppose the registers 0x4 and 0x5 in the Vole...Ch. 2 - Prob. 33CRPCh. 2 - Prob. 34CRPCh. 2 - Prob. 35CRPCh. 2 - Prob. 36CRPCh. 2 - Prob. 37CRPCh. 2 - Prob. 38CRPCh. 2 - Prob. 39CRPCh. 2 - Prob. 40CRPCh. 2 - Prob. 41CRPCh. 2 - Prob. 42CRPCh. 2 - a. What single instruction in the Vole machine...Ch. 2 - Write a Vole program that reverses the contents of...Ch. 2 - Write a Vole program that subtracts the value...Ch. 2 - Prob. 46CRPCh. 2 - Suppose a person is typing forty words per minute...Ch. 2 - Prob. 48CRPCh. 2 - Suppose the Vole communicates with a printer using...Ch. 2 - Write a Vole program that places 0s in all the...Ch. 2 - Prob. 51CRPCh. 2 - Prob. 52CRPCh. 2 - Suppose you are given 32 processors, each capable...Ch. 2 - Prob. 54CRPCh. 2 - Prob. 55CRPCh. 2 - Describe how the average of a collection of...Ch. 2 - Write and test a Python script that reads in a...Ch. 2 - Write and test a Python script that reads in a...Ch. 2 - Prob. 59CRPCh. 2 - Suppose a computer manufacturer develops a new...Ch. 2 - Prob. 2SICh. 2 - Prob. 3SICh. 2 - Prob. 4SICh. 2 - Suppose a manufacturer produces a computer chip...Ch. 2 - Prob. 6SICh. 2 - Prob. 7SICh. 2 - Prob. 8SI
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- What are the drawbacks of using MIPS or FLOPS as a system throughput metric?arrow_forwardGiven that a bus has 64 data lines and requires 4 cycles of 125 nanoseconds each to transfer data. The bandwidth of this bus is 16 Megabytes/sec. If the cycle time of the bus is increased to 180 nanoseconds and the number of cycles required for transfer is the same, calculate bus bandwidth for the case above.arrow_forward2. Suppose that we are given 32KB SRAM ICs and 8KB ROM ICs. We want to construct the address range for RAM to be from 00000H to 3FFFFH, and from 80000H to 8FFFFH. We also want to construct the address range for ROM to be from FC000H to FFFFFH. Show a possible address decoding circuit.arrow_forward
- DMA transfers 8 bits in one CPU cycle at regular intervals. For a 2 Mhz processor, if CPU uses 0.4% processor cycles for DMA, determine the data transfer rate in bits per second.arrow_forward5. Consider three different processors P1, P2, and P3 executing the sameinstruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHzclock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2.Which processor has the highest performance expressed in instructions persecond?arrow_forwardAssume you want to use Timer 1 to generate a mode 6 (9 bit Fast mode PWM) signal. What is the highest frequency you can produce (shortest delay) given that the CPU clock is 8MHZ? (Note: Answer should be in Hz) Answer:arrow_forward
- 4. bus throughput Consider a serial bus (1 bit wide) that runs at 2GHZ, usingalternate cycles for control signals and the other half of the cycles for data. What is the throughput of the busin bytes/second? Assume you wantto attach a video camera using this bus. The camera generates 60 frames per second, with each frame containing 1 Million pixels, each pixel 4 bytes in size. Would this work? Answer one of the below: a) If not, what compression factor would the camera need to achieve to be supported? A compression factor describes how mu ch smaller the data is when compared to un- compressed data. b) If yes, how many cameras could be connected?arrow_forward4. Consider two systems S₁ and S₂ in which at most 25% of S₁ can be improved and its performance can be tripled, while at most 75% of S₂ can be improved and its performance can be doubled. Determine the speedup ratios for S, and S₂.arrow_forwardDMA transfers 8 bits in 1 CPU cycle at regular intervals. For a 2 Mhz processor, if CPU uses 0.6% processor cycles for DMA, determine the data transfer rate in bits per second.arrow_forward
- Discuss the difference between single-ended and differential bus operation.arrow_forwardConsider a datapath with 6 stages. Operation times/delays associated with each of these 6 stages are shown below: Register Write Back Instruction Instruction Execute 1 Execute 2 Data Access Fetch 200 ps Decode 100 ps 150 ps 150 ps 200 ps 100 ps Answer the following questions: a) What is the shortest possible clock period for single-cycle, non-pipelined implementation? What is the shortest possible clock period for pipelined implementation? How long will it take to execute 5 instructions on single-cycle, non-pipelined implementation? How long will it take to execute 5 instructions on pipelined implementation? Assume that no pipeline hazards are encountered while executing these 5 instructions. How long will it take to execute 5 instructions on pipelined implementation? Assume that there are 2 pipeline stalls (due to hazards) while executing these 5 instructions. b) c) d) e)arrow_forwardA gaming device has to transfer a high definition 1280 x 720 x 3 video frame @ 30 frames/sec. The 32-bit system bus operates at 100MHz clock. It takes one clock cycle to make one transfer through the bus (i.e. D=1) and there is an overhead of ten clock cycles per transfer (i.e. O=10) Is this bus suitable for this system? If not, then what can be done to make it suitable? Explain. What if the bus operates in burst mode (burst size of 4)? Would it be suitable to use? Explain.arrow_forward
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