Chapter 13, Problem 13.10TYU

To determine

The maximum and minimum output voltage in the MC14573 circuit such that op-amp remains biased in its linear region.

Answer to Problem 13.10TYU

The input common mode voltage range for the MC14573 op-amp is

  $-4.75\le v_o\le 4.6\text{V}$ .

Explanation of Solution

Given:

Following is given circuit of the MC14573 op-amp equivalent circuit

  

Given data,

The transistor parameters are

  $\left|V_T\right|=0.5\text{V}$ (all transistors)

  $k_n^{\prime }=100\mu \text{A}/{\text{V}}^2$

  $k_p^{\text{'}}=40\mu \text{A}/{\text{V}}^2$

And the circuit parameters are

$V^{+}=5\text{V}$

  $V^{+}=-5\text{V}$

  $R_{set}=225\text{kΩ}$

The given width to length ratio of ${\left(\frac{W}{L}\right)}_{3,A}$ is 6.25 for transistor $M_3$ and $M_4$ and

  $\frac{W}{L}=12.5$ for all other transistor.

Calculation:

For transistors $M_5$ and $M_6,$ the conduction parameters are

  $\begin{array}{l}{K}_P=\left(\frac{k_p^{\prime }}{2}\right){\left(\frac{W}{L}\right)}_5\\ =\left(\frac{40\times {10}^{-6}}{2}\right)(12.5)=\left(20\times {10}^{-6}\right)(12.5)\\ K_P=0.25\times {10}^{-3}\end{array}$

Hence, $K_{p5}=K_{p6}=0.25\text{mA}/{\text{V}}^2$

Now assuming the transistor $M_5$ and $M_6$ are matched, the reference and input stage bias

currents are given as

  $I_{\text{set}}=I_Q=\frac{V^{\ast }-V^{-}-V_{\text{scs}}}{R_{\text{vet}}}\dots \dots (1)$

We know that the reference current and source to gate voltage is also related by

  $I_{s\text{st}}=K_{p5}{\left(V_{sos}+V_{tr}\right)}^2\dots \dots (2)$

Now combining equation (1) and (2) yields the source to gate voltage of $M_5$

  $K_{PS}{\left(V_{SGS}+V_{TP}\right)}^2=\frac{V^{+}-V^{-}-V_{SGS}}{R_{set}}$

  $\begin{array}{l}0.25\times {10}^{-3}{\left(V_{SGS}-0.5\right)}^2=\frac{5-(-5)-V_{SGS}}{225\times {10}^3}\hfill \\ 0.25\times {10}^{-3}{\left(V_{SGS}-0.5\right)}^2=\frac{10-V_{SGS}}{225\times {10}^3}\hfill \\ \left(0.25\times {10}^{-3}\right)\left(225\times {10}^3\right){\left(V_{SGS}-0.5\right)}^2=10-V_{SGS}\hfill \end{array}$

  $\begin{array}{l}56.25{\left(V_{SGS}-0.5\right)}^2=10-V_{SGS}\hfill \\ 56.25\left(V_{SGS}^2-V_{SGS}+0.25\right)=10-V_{SGS}\hfill \\ 56.25V_{SGS}^2-56.25V_{SGS}+14.0625=10-V_{SGS}\hfill \\ 56.25V_{SGS}^2-55.25V_{SGS}+4.0625=0\hfill \end{array}$

Using quadratic equation,

  $\begin{array}{l}{V}_{SGS}=\frac{-(-55.25)\pm \sqrt{{(-55.25)}^2-4\times 56.25\times 4.0625}}{2\times 56.25}\\ =\frac{55.25\pm \sqrt{2138.5}}{112.5}\\ V_{SGS}=\frac{55.25\pm 46.244}{112.5}\\ V_{SGS}=\frac{55.25+46.244}{112.5}\\ =\frac{101.494}{112.5}\\ V_{SGS}=0.9022\end{array}$

Hence, $V_{SGS}=0.9022$

Now from equation (1) we have

  $\begin{array}{l}{I}_{\text{set}}=I_Q=\frac{V^{\ast }-V^{-}-V_{SGS}}{R_{set}}\\ =\frac{5-(-5)-0.9022}{225\times {10}^3}\\ =\frac{10-0.9022}{225\times {10}^3}=\frac{9.0978}{225\times {10}^3}\\ I_{\text{set}}=40.4\times {10}^{-6}\end{array}$

The reference current is $I_{\mathrm{R}EF}=I_Q=40.4\mu \text{A}$ .

Similarly, the source to gate voltage of $M_6$ we get as $V_{SGS}=V_{SG6}=0.9\text{V}$ .

We know that

  $\begin{array}{cc}{V}_{SDS}(\text{sat})=V_{SG6}+V_{TP}& \\ =0.9-0.5& \\ V_{SD6}(\text{sat})=0.4& \end{array}$

Therefore, the source-to-drain saturation voltage is $V_{SD6}(\text{sat})=0.4\text{V}$ .

Now the maximum input voltage is given as

  $\begin{array}{l}{v}_o(\max )=V^{+}-V_{SD6}(sat)\\ =5-0.4\\ v_o(\max )=4.6\end{array}$

Therefore, the maximum input voltage is $v_o(\max )=4.6$ .

Now for transistor $M_4$

  $\begin{array}{l}{K}_{p3}=\left(\frac{k_n^{\prime }}{2}\right){\left(\frac{W}{L}\right)}_3\\ =\left(\frac{100\times {10}^{-6}}{2}\right)(6.25)\\ =\left(50\times {10}^{-6}\right)(6.25)\\ K_{p3}=312.5\times {10}^{-6}\end{array}$

Therefore, $K_{p3}=312.5\mu \text{A}$

Now

  $I_{D3}=K_{p3}{\left(V_{SG3}+V_{TP}\right)}^2$

Where $I_{D3}=\frac{I_Q}{2}$

Now $\frac{I_Q}{2}=K_{p3}{\left(V_{SG3}+V_{TP}\right)}^2$

  $\frac{I_Q}{2}=K_{\rho 3}{\left(V_{SG3}+V_{TP}\right)}^2$

  $\frac{40.4\times {10}^{-6}}{2}=\left(312.5\times {10}^{-6}\right){\left(V_{SG3}-0.5\right)}^2$

  $0.06464={\left(V_{SG3}-0.5\right)}^2$

  $\sqrt{0.06464}=\left(V_{SG3}-0.5\right)$

  $0.254=V_{SG3}-0.5$

  $V_{SG3}=0.754$

Therefore, the source-to-gate voltage of $M_3$ is $V_{SG3}=0.754\text{V}$ .

We know that

  $\begin{array}{l}{V}_{\text{SD1}}(\text{sat})=V_{SG3}+V_{TP}\\ =0.754-0.5\\ V_{SD1}(\text{sat})=0.254\end{array}$

Therefore, the source-to-drain saturation voltage is $V_{SD1}(\text{sat})=0.254\text{V}$ .

Now the minimum input voltage is given as

  $\begin{array}{l}{v}_o(\min )=V^{-}+V_{GS3}+V_{SD1}(\text{sat})-V_{SG4}\\ =-5+0.754+0.254-0.754\\ =-5+0.254\\ v_o(\min )=-4.75\end{array}$

Therefore, the minimum input voltage is $v_o(\min )=-4.75\text{V}$ .

The input common mode voltage range for the MC14573 op-amp is

  $-4.75\le v_o\le 4.6\text{V}$ .