a 8 msb/ AND XOR 9 AND -U3 AND N b -8 16 хор Uz EFACEFACEFACEFACEFACEFALEFACEFA P A-EFA-EFA-EFA-EFA о 9 Sj XOR Po P 17 Pz AND P3 U. 08 EFAL 04 to 5 07 34 /aOR MSB MAX -8 Ur ⚫ your circuit diagrams for your basic bricks, such as AND, OR, XOR gates and 1 bit multiplexers, ⚫ your circuit diagrams for your extended full adder, designed in Section 1 and ⚫ your circuit diagrams for your 8-bit arithmetical-logical unit, designed in Section 2. 1 An Extended Full Adder In this Section, we are going to design an extended full adder circuit (EFA). That EFA takes 6 one bit inputs: aj, bj, Cin, Tin, t₁ and to. Depending on the four possible combinations of values on t₁ and to, the EFA produces 3 one bit outputs: sj, Cout and rout. The EFA can be specified in principle by a truth table with 26 = 64 entries and 3 outputs. However, as the EFA ignores certain inputs in certain cases, it is easier to work with the following overview specification, depending only on t₁ and to in the first place: t₁ to Description 00 Output Relationship Ignored Inputs Addition Mode 2 Coutsjaj + bj + Cin, Tout= 0 Tin 0 1 Shift Left Mode Sj = Cin, Cout=bj, rout = 0 rin, aj 10 1 1 Shift Right Mode Logical Mode S; = Tin, Tout = bj, Cout 0 Cin, aj (Cin ^ (a; ® b;)) V (Cin ^ (aj V bj)), Cout = Cin, Tout = 0 | Tin In this table above, Cin stands for the inverted Cin signal, A stands for the logical AND of two bits, V stands for the logical OR of two bits and stands for the logical XOR² of two bits. Design a circuit for EFA based on this specification with nothing but two bit input-one bit output NAND gates. If you wish to use other types of gates, such as AND gates, OR gates, XOR gates, you can design them first and then instantiate them in your EFA diagram. If you wish to use Disjunctive Normal Form, you can do so, but you need to give the full 64 entry truth table first in this case. Test your circuit on at least 8 (eight) different input patterns. You can do the testing by propagating the signals (zeros and ones) across the different wires it contains. You can use eight different colors in the same drawing, unless this becomes too messy. 2 An 8-bit Arithmetical-Logical Unit Based on circuitry for sign- resp. zero-extension (signed resp. unsigned numbers), XOR units to flip input bits, AND units to set inputs to zero, nine EFA circuits, XOR units in output and units for signed comparison with zero, we will now design a full 8-bit Arithmetical-Logical Unit (ALU). This ALU unit will take to 8-bit inputs a and b (with bits a7 through ao and by through bo, where the bit with index O is the least significant bit), as well as a 4-bit steering input p (with bits p3 through po) and it will produce an 8-bit output c (with bits c7 through co). The input/output relationship is specified by the following table: Cin = 1 if Cin = 0 and Cin = 0 if Cin = 1 2XOR = exclusive OR Ignored inputs P3 P2 P1 Po Description 0000 000 1 0010 00 1 1 0 100 0101 0 1 1 0 0 1 1 1 Addition Subtraction Shift Left Compare LTU Shift Right Logical Compare LEU Logical XOR Logical OR Corresponding C code c = a + b c = a - b с = b << 1 с = (a < b) cb >> 1 с (a <= b) с = a ^ b cab (a==b) Туре signed & unsigned signed & unsigned signed & unsigned a - a unsigned unsigned unsigned signed & unsigned - signed & unsigned signed & unsigned 1 0 10 0 0 Compare EQ 0 1 Unary Minus с = -b 1 0 1 0 Compare NEQ C = 1 0 1 1 1 1 00 Compare LT c (a != b) (ab) signed & unsigned a signed & unsigned signed - Shift Right Arithmetical c = 1 1 0 1 Compare LE с 1 110 1 1 1 1 Logical Negation Logical AND b >> 1 (a <= b) b c = a & b signed signed signed & unsigned a signed & unsigned Design such an ALU, based on your previous basic bricks, in particular based on nine instances of your EFA brick. If you need to generate intermediate steering signals, give truth tables for these signals and circuits to generate these steering signals. You are not supposed to design circuits for the different operations on 8 bits and then use a big multiplexer; you are rather supposed to use the EFA brick 8 or 9 times. Test your ALU for each of of the 16 possible combinations of p and for at least one interesting input combi- nation of a and b. Use several colors and several drawings.

Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter4: Processor Technology And Architecture
Section: Chapter Questions
Problem 9VE
icon
Related questions
Question
a
8
msb/
AND
XOR
9
AND
-U3
AND
N
b
-8
16
хор
Uz
EFACEFACEFACEFACEFACEFALEFACEFA
P
A-EFA-EFA-EFA-EFA
о
9
Sj
XOR
Po
P
17
Pz
AND
P3
U.
08
EFAL
04
to
5
07
34
/aOR
MSB
MAX
-8
Ur
Transcribed Image Text:a 8 msb/ AND XOR 9 AND -U3 AND N b -8 16 хор Uz EFACEFACEFACEFACEFACEFALEFACEFA P A-EFA-EFA-EFA-EFA о 9 Sj XOR Po P 17 Pz AND P3 U. 08 EFAL 04 to 5 07 34 /aOR MSB MAX -8 Ur
⚫ your circuit diagrams for your basic bricks, such as AND, OR, XOR gates and 1 bit multiplexers,
⚫ your circuit diagrams for your extended full adder, designed in Section 1 and
⚫ your circuit diagrams for your 8-bit arithmetical-logical unit, designed in Section 2.
1 An Extended Full Adder
In this Section, we are going to design an extended full adder circuit (EFA). That EFA takes 6 one bit inputs: aj, bj,
Cin, Tin, t₁ and to. Depending on the four possible combinations of values on t₁ and to, the EFA produces 3 one bit
outputs: sj, Cout and rout.
The EFA can be specified in principle by a truth table with 26 = 64 entries and 3 outputs. However, as the EFA
ignores certain inputs in certain cases, it is easier to work with the following overview specification, depending only
on t₁ and to in the first place:
t₁ to Description
00
Output Relationship
Ignored
Inputs
Addition Mode
2 Coutsjaj + bj + Cin, Tout= 0
Tin
0 1
Shift Left Mode
Sj = Cin,
Cout=bj, rout = 0
rin, aj
10
1 1
Shift Right Mode
Logical Mode
S; = Tin, Tout = bj, Cout 0
Cin, aj
(Cin ^ (a; ® b;)) V (Cin ^ (aj V bj)), Cout = Cin, Tout = 0 | Tin
In this table above, Cin stands for the inverted Cin signal, A stands for the logical AND of two bits, V stands for the
logical OR of two bits and stands for the logical XOR² of two bits.
Design a circuit for EFA based on this specification with nothing but two bit input-one bit output NAND
gates. If you wish to use other types of gates, such as AND gates, OR gates, XOR gates, you can design them first
and then instantiate them in your EFA diagram. If you wish to use Disjunctive Normal Form, you can do so, but you
need to give the full 64 entry truth table first in this case.
Test your circuit on at least 8 (eight) different input patterns. You can do the testing by propagating the signals
(zeros and ones) across the different wires it contains. You can use eight different colors in the same drawing, unless
this becomes too messy.
2 An 8-bit Arithmetical-Logical Unit
Based on circuitry for sign- resp. zero-extension (signed resp. unsigned numbers), XOR units to flip input bits, AND
units to set inputs to zero, nine EFA circuits, XOR units in output and units for signed comparison with zero, we will
now design a full 8-bit Arithmetical-Logical Unit (ALU).
This ALU unit will take to 8-bit inputs a and b (with bits a7 through ao and by through bo, where the bit with index
O is the least significant bit), as well as a 4-bit steering input p (with bits p3 through po) and it will produce an 8-bit
output c (with bits c7 through co).
The input/output relationship is specified by the following table:
Cin = 1 if Cin = 0 and Cin = 0 if Cin = 1
2XOR = exclusive OR
Ignored
inputs
P3 P2 P1 Po Description
0000
000 1
0010
00 1 1
0 100
0101
0 1 1 0
0 1 1 1
Addition
Subtraction
Shift Left
Compare LTU
Shift Right Logical
Compare LEU
Logical XOR
Logical OR
Corresponding
C code
c = a + b
c = a - b
с = b << 1
с = (a < b)
cb >> 1
с
(a <= b)
с = a ^ b
cab
(a==b)
Туре
signed & unsigned
signed & unsigned
signed & unsigned a
-
a
unsigned
unsigned
unsigned
signed & unsigned
-
signed & unsigned
signed & unsigned
1 0
10
0
0
Compare EQ
0
1
Unary Minus
с
= -b
1 0 1 0
Compare NEQ
C =
1 0
1 1
1 1
00
Compare LT
c
(a != b)
(ab)
signed & unsigned a
signed & unsigned
signed
-
Shift Right Arithmetical
c =
1 1 0 1
Compare LE
с
1
110
1
1 1 1
Logical Negation
Logical AND
b >> 1
(a <= b)
b
c = a & b
signed
signed
signed & unsigned a
signed & unsigned
Design such an ALU, based on your previous basic bricks, in particular based on nine instances of your EFA
brick. If you need to generate intermediate steering signals, give truth tables for these signals and circuits to generate
these steering signals. You are not supposed to design circuits for the different operations on 8 bits and then use a big
multiplexer; you are rather supposed to use the EFA brick 8 or 9 times.
Test your ALU for each of of the 16 possible combinations of p and for at least one interesting input combi-
nation of a and b. Use several colors and several drawings.
Transcribed Image Text:⚫ your circuit diagrams for your basic bricks, such as AND, OR, XOR gates and 1 bit multiplexers, ⚫ your circuit diagrams for your extended full adder, designed in Section 1 and ⚫ your circuit diagrams for your 8-bit arithmetical-logical unit, designed in Section 2. 1 An Extended Full Adder In this Section, we are going to design an extended full adder circuit (EFA). That EFA takes 6 one bit inputs: aj, bj, Cin, Tin, t₁ and to. Depending on the four possible combinations of values on t₁ and to, the EFA produces 3 one bit outputs: sj, Cout and rout. The EFA can be specified in principle by a truth table with 26 = 64 entries and 3 outputs. However, as the EFA ignores certain inputs in certain cases, it is easier to work with the following overview specification, depending only on t₁ and to in the first place: t₁ to Description 00 Output Relationship Ignored Inputs Addition Mode 2 Coutsjaj + bj + Cin, Tout= 0 Tin 0 1 Shift Left Mode Sj = Cin, Cout=bj, rout = 0 rin, aj 10 1 1 Shift Right Mode Logical Mode S; = Tin, Tout = bj, Cout 0 Cin, aj (Cin ^ (a; ® b;)) V (Cin ^ (aj V bj)), Cout = Cin, Tout = 0 | Tin In this table above, Cin stands for the inverted Cin signal, A stands for the logical AND of two bits, V stands for the logical OR of two bits and stands for the logical XOR² of two bits. Design a circuit for EFA based on this specification with nothing but two bit input-one bit output NAND gates. If you wish to use other types of gates, such as AND gates, OR gates, XOR gates, you can design them first and then instantiate them in your EFA diagram. If you wish to use Disjunctive Normal Form, you can do so, but you need to give the full 64 entry truth table first in this case. Test your circuit on at least 8 (eight) different input patterns. You can do the testing by propagating the signals (zeros and ones) across the different wires it contains. You can use eight different colors in the same drawing, unless this becomes too messy. 2 An 8-bit Arithmetical-Logical Unit Based on circuitry for sign- resp. zero-extension (signed resp. unsigned numbers), XOR units to flip input bits, AND units to set inputs to zero, nine EFA circuits, XOR units in output and units for signed comparison with zero, we will now design a full 8-bit Arithmetical-Logical Unit (ALU). This ALU unit will take to 8-bit inputs a and b (with bits a7 through ao and by through bo, where the bit with index O is the least significant bit), as well as a 4-bit steering input p (with bits p3 through po) and it will produce an 8-bit output c (with bits c7 through co). The input/output relationship is specified by the following table: Cin = 1 if Cin = 0 and Cin = 0 if Cin = 1 2XOR = exclusive OR Ignored inputs P3 P2 P1 Po Description 0000 000 1 0010 00 1 1 0 100 0101 0 1 1 0 0 1 1 1 Addition Subtraction Shift Left Compare LTU Shift Right Logical Compare LEU Logical XOR Logical OR Corresponding C code c = a + b c = a - b с = b << 1 с = (a < b) cb >> 1 с (a <= b) с = a ^ b cab (a==b) Туре signed & unsigned signed & unsigned signed & unsigned a - a unsigned unsigned unsigned signed & unsigned - signed & unsigned signed & unsigned 1 0 10 0 0 Compare EQ 0 1 Unary Minus с = -b 1 0 1 0 Compare NEQ C = 1 0 1 1 1 1 00 Compare LT c (a != b) (ab) signed & unsigned a signed & unsigned signed - Shift Right Arithmetical c = 1 1 0 1 Compare LE с 1 110 1 1 1 1 Logical Negation Logical AND b >> 1 (a <= b) b c = a & b signed signed signed & unsigned a signed & unsigned Design such an ALU, based on your previous basic bricks, in particular based on nine instances of your EFA brick. If you need to generate intermediate steering signals, give truth tables for these signals and circuits to generate these steering signals. You are not supposed to design circuits for the different operations on 8 bits and then use a big multiplexer; you are rather supposed to use the EFA brick 8 or 9 times. Test your ALU for each of of the 16 possible combinations of p and for at least one interesting input combi- nation of a and b. Use several colors and several drawings.
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