The objective of this laboratory is to get students familiar with basic MC8051 timing / counting operation with Gate in association with the two external hardware interrupts. Laboratory Requirements: Write an assembly logic program using the two timers in mode 1 with Gate and maximum delay. Analyze the logic and confirm it performs the following: • TO stops and retains its count while INTO is being served. T1 does the same while INT1 is being served. ⚫ INTO interrupt displays PO increment on P1 and INT1 interrupt displays PO complement on P2. ⚫ TO overflow will complement P3.0 and T1 overflow will complement P3.1. • Describe the process details as documented in the program. ⚫ Document your work including process description, design, implementation, and proof of debugging.

The objective of this laboratory is to get students familiar with basic MC8051 timing / counting operation with Gate in association with the two external hardware interrupts. Laboratory Requirements: Write an assembly logic program using the two timers in mode 1 with Gate and maximum delay. Analyze the logic and confirm it performs the following: • TO stops and retains its count while INTO is being served. T1 does the same while INT1 is being served. ⚫ INTO interrupt displays PO increment on P1 and INT1 interrupt displays PO complement on P2. ⚫ TO overflow will complement P3.0 and T1 overflow will complement P3.1. • Describe the process details as documented in the program. ⚫ Document your work including process description, design, implementation, and proof of debugging.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 14VE

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