7. Consider the fragment of RISC-V assembly code belowsdx29, 12(x16)x29, 8(x16)х17, х15, х14Idsubbeqzaddx17, labelх15, х11, х14х15, х30, х14х2, х3, -1subaddi//implements x2 = x3 - 1addX2, х2, х5Suppose we modify the pipeline so that it has only one memory (that handles bothinstructions and data). In this case there will be structural hazard every time a program needsto fetch an instruction during the same cycle in which another instruction access the data.How many stall cycles are introduced in the code due to structural hazards?--Ans:

x29, 12(x16) x29, 8(x16) х17, х15, х14 x17, label х15, х11, х14 ub zba d ub ddi d х15, х30, х14 х2, х3, -1 //implements x2 = x3 - 1 х2, х2, х5 uppose we modify the pipeline so that it has only one memory (that structions and data). In this case there will be structural hazard every time a fetch an instruction during the same cycle in which another instruction acc

x29, 12(x16) x29, 8(x16) х17, х15, х14 x17, label х15, х11, х14 ub zba d ub ddi d х15, х30, х14 х2, х3, -1 //implements x2 = x3 - 1 х2, х2, х5 uppose we modify the pipeline so that it has only one memory (that structions and data). In this case there will be structural hazard every time a fetch an instruction during the same cycle in which another instruction acc

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Question

7. Consider the fragment of RISC-V assembly code below
sd
x29, 12(x16)
x29, 8(x16)
х17, х15, х14
Id
sub
beqz
add
x17, label
х15, х11, х14
х15, х30, х14
х2, х3, -1
sub
addi
//implements x2 = x3 - 1
add
X2, х2, х5
Suppose we modify the pipeline so that it has only one memory (that handles both
instructions and data). In this case there will be structural hazard every time a program needs
to fetch an instruction during the same cycle in which another instruction access the data.
How many stall cycles are introduced in the code due to structural hazards?--
Ans:

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Answser must be in MIPSzy assembly language. Max of 3 - Branch
3 C language into LC-3 Assembly Language
Consider the fragment of LEGv8 assembly below: Program1 STUR X16, [X6, #12] LDUR X16, [X6, #8] SUB X7, X5, X4 CBZ X7, Label ADD X5, X1, X4 SUB X5, X15, X4 Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data. 1- Draw a pipeline diagram to show where the code above will stall. 2- In general, is it possible to reduce the number of stalls/ NOPs resulting from this structural hazard by reordering code (reordering the instructions)? 3- Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPs to the code. Can you do the same with this structural hazard? If so, explain how. If not, explain why not. 4- If we run the code above on a single-cycle computer, what kind of hazards are there? Student should write a justification…
Given loop: LOOP: LDUR X10, [X1, #0] LDUR X11, [X1, #8] ADD X12, X10, X11 SUBI X1, X1, #16 CBNZ X12, LOOP 1) Assume that perfect branch prediction is used (no stall due to control hazard), that has full forwarding support, and that branches are resolved in ID stage. Show a pipeline execution time diagram for the first two iterations of this loop. 2) Assume branches are predicted as not-taken (but actually taken) the first time and predicted taken (but actually not-taken) the second time. Assume full forwarding support and that branches are resolved in EX stage. Show the execution time diagram for the first two iterations of this loop.