With respect to the 2-bit branch prediction strategy to mitigate stalls due to a control hazard, if the current state is 01, and the actual outcome for the branch is taken. What is the updated state of the predictor. (1 Point) * M 00 01 10 11
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- on on on on A 4-bit carry look-ahead adder and a 64-bit carry look-ahead adder have the same complexity Select one: O True O False Select the correct answer of the BCD addition of: 205+147 Select one: O a. 001101010010 O b. 110001110101 O c. 100111110101 O d. 100001111101 Verilog is a hardware descriptive language that is easier than VHDL. Select one: O True O False In VHDL, a signal's name can only start and contain characters. Select one: O True O FalseDraw the finite state automaton diagram for a 2-bit branch history predictor that changes prediction after two consecutive incorrect predictions.Write VHDL code for a modulo-13 counter (counting sequence is 010, 110, …. 1210). The counter has the following features: an asynchronous Active High Reset a value R can be loaded into the counter, using the signal Ld (Load) The signal Ld is active High Draw the schematic of your counter, showing the inputs and outputs. Show the number of bits for R, Q (output of the counter), Ld.
- Write VHDL code for a modulo-13 counter (counting sequence is 010, 110, …. 1210). The counter has the following features: an asynchronous Active Low Reset a value R can be loaded into the counter, using the signal Ld (Load) The signal Ld is active Low Draw the schematic of your counter, showing the inputs and outputs. Show the number of bits for R, Q (output of the counter), Ld.Q2. Using 74LS163 4-bit binary counter and any nessary gates, design a counter that produces the count sequence: 0, 1, 2, 10, 11, 12 and 13, and repeats. 74x163 > CLK CLR LD Inputs ENP Outputs QD QC QB QA| QD* QC* QB* QA* Current State ENT CLR L LD L ENT ENP RCO* 14 QA 13 QB 12 X B 1 B A 11 QD QD QD 1 QC QC QB QB 1 QA RCO 1 1 QA Solution:An automated water tank system consists of Flash ADC, DAC, sensor and motor where sensor gives voltage value as output. If the water level of the tank goes below 15%, it produces the voltage of 5.10V. That voltage is then put through a 4-bit Flash ADC as input (where reference voltage is 16V and R=5kΩ). After that the output of that ADC applied to a Binary Weighted DAC (where the “logic 1” as 5 V, “logic 0” as 0 V and R = 3.5kΩ) to produce sufficient voltage to turn ON the water supply motor. i. Draw the block diagram of the whole system ii. Design the complete circuit diagram (combined) of the system consisting ADC and DAC. iii. Find the required voltage to turn ON the motor.
- Consider a special purpose decoder that is called BCD to seven-segment decoder. The decoder takes a 4-bit Binary Coded Decimal (BCD) number X3 X2 X4 X0 (0-9) and produces 7 outputs a, b, c, d, e, f, and g The specification of this circuit is as follows: ⚫ The 7 outputs of the decoder are connected to LED segments as shown in the figure below. The LEDs are active low, ie, the LED emits light when it is connected to logic 0. • The decoder output is determined in a way so that the LED segments display the decimal representation of the input. For example, if the input X3 X2 X1 X0 is 0001 respectively (which is equivalent to decimal 1), the outputs a, b, c, d, e, f, and gare 1001111 showing the letter 1 on the display (remember the LEDs are active low). Decoder W- 4x7 e U Answer the following questions: a. Fill in the truth table of that decoder. Choose a good value for the output when the input is greater than decimal 9. b. Derive the simplified Boolean expressions for the outputs a, b, c,…Use VHDL to implement a 16-to-1 Multiplexer. The inputs are w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, and w11. The last four inputs are not attached to an input signal. How many select bits need the circuit?Please answer all the questions
- The state table shown in Table 3 is for a sequential synchronous circuit. Choose a specific encoding and assignment for the states, and complete the equations of excitation and design for the circuit using type D and S-R flipflops. Present Next State Yield State * = Y2Y1Y0 Y,Y1Y0 Y½Y1Y x = 0 = 1 A В A В A 1 C D A D D E 1 E C 1 1 Table 3: State Table Question 3aDesign a Mealy-type FSM that detects a sequence of four or more consecutive 1's in a string of bits coming through an input line. Draw out the state diagram, the state table, and state-assigned table; then, synthesize the circuit. An example of the desired behavior is: w: 0011110111110 z: 0000010000110A combinational circuit is divided into two sub-circuits N1 and N2 as shown. The truth table for N1 is given. Assume that the input combinations ABC = 111 and ABC=000 never occur. 1- Complete the truth table. 2- Write D as minterms expansion and F as Maxterms expansion (Decimal notation). 3- Determine the Boolean expression of Z in terms of D, E and F as Maxterms expansion (Decimal notation). 4- Simplify the expressions of D, E and F as minimum Products of Sum. 5- Design the circuit of N₁ as minimum NOR-NOR implementation. 0 0 0 0 A B- C- ABC D E 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 N₁ 0 [1] F 1 1 1 1 0 1 0 1 0 1 1 0 0 0 1 D E F N N₂ Z