(c) (d) discuss the test result data and possible faults if it fails this test. comment on what manufacturers could do to implement quality management systems, aiming to reduce failure rate and improve testability of electronic products. marks) The TAP Controller state diagram is supplied in Figure 2. The current state is unknown. тск о TMS O D E A O с IC1 F B A G H TDI TDO TMS TCK W X Figure 1 Circuit diagram The instruction code set for IC1 is shown in the table below. Instruction OPCODE MSB LSB SAMPLE 1 0 1 INTEST 0 1 0 BYPASS 1 1 1 EXTEST 0 1 1 0 TLreset 0 Run-Test/Idle Y 1 Select DR 0 1 Select IR 0 Capture DR Capture IR 0 0 Shift DR Shift IR 0 0 Exit-1 DR 1 Exit-1 IR 1 0 0 Pause DR Pause IR 1 0 0 0 Exit-2 DR Exit-2 IR Update DR 1 0 Update IR 0 Figure 2 State diagram of the TAP controller Further information IC1 is an IEEE1149.1 compatible 8-port boundary scan device, where ports A to D are inputs and ports E to H are the corresponding outputs. A to H serially follow a path starting at TDI and finishing at TDO. The test procedure should show: the Clock Cycle, TDI, TMS, TDO, the Current State, the Next State and the current Instruction. Assume IC1 has an identity register but does not have external reset capability (e.g. no TRST). (c) (d) discuss the test result data and possible faults if it fails this test. comment on what manufacturers could do to implement quality management systems, aiming to reduce failure rate and improve testability of electronic products. marks) The TAP Controller state diagram is supplied in Figure 2. The current state is unknown. тск о TMS O D E A O с IC1 F B A G H TDI TDO TMS TCK W X Figure 1 Circuit diagram The instruction code set for IC1 is shown in the table below. Instruction OPCODE MSB LSB SAMPLE 1 0 1 INTEST 0 1 0 BYPASS 1 1 1 EXTEST 0 1 1 0 TLreset 0 Run-Test/Idle Y 1 Select DR 0 1 Select IR 0 Capture DR Capture IR 0 0 Shift DR Shift IR 0 0 Exit-1 DR 1 Exit-1 IR 1 0 0 Pause DR Pause IR 1 0 0 0 Exit-2 DR Exit-2 IR Update DR 1 0 Update IR 0 Figure 2 State diagram of the TAP controller Further information IC1 is an IEEE1149.1 compatible 8-port boundary scan device, where ports A to D are inputs and ports E to H are the corresponding outputs. A to H serially follow a path starting at TDI and finishing at TDO. The test procedure should show: the Clock Cycle, TDI, TMS, TDO, the Current State, the Next State and the current Instruction. Assume IC1 has an identity register but does not have external reset capability (e.g. no TRST).