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Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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Question

What are the worst-case values of τ_PHL and τ_PLH
for the gate in Fig. when it is implemented
using only 2/1 transistors and drives a load capacitance
of 0.5 pF? Assume V_DD =2.5 V.

Expert Solution

Step 1

Considering given CMOS gate

Calculating propagation delay from low to high for NMOS sub-network

Given C = 0.5 pF, V_DD = 2.5, V_TN = 0.6 V, W/L = (2/1)

$τ_{P H L} = 1.2 R_{o n n} C$

On resistance of NMOS

$R_{o n n} = \frac{1}{K_{n}' {(\frac{W}{L})}_{N} (V_{D D} - V_{T N})}$

Step 2

In the worst condition output will be low due to three NMOS connected in series

$τ_{P H L} = \frac{1.2 C}{K_{n}' {(\frac{W}{L})}_{N} (V_{D D} - V_{T N})} τ_{P H L} = \frac{1.2 \times 0.5 \times 10^{- 12}}{(100 μ A / V^{2}) (\frac{2}{3}) (2.5 V - 0.6 V)} τ_{P H L} = \frac{1.2 \times 0.5 \times 10^{- 12}}{(100 \times 10^{- 6} A / V^{2}) (\frac{2}{3}) (2.5 V - 0.6 V)} τ_{P H L} = 4.74 n s$

Step 3

Only one transistor will conduct in minimum worst case, W/L is (2/1)

$τ_{P H L} = \frac{1.2 C}{K_{n}' {(\frac{W}{L})}_{N} (V_{D D} - V_{T N})} τ_{P H L} = \frac{1.2 \times 0.5 \times 10^{- 12}}{(100 μ A / V^{2}) (\frac{2}{1}) (2.5 V - 0.6 V)} τ_{P H L} = \frac{1.2 \times 0.5 \times 10^{- 12}}{(100 \times 10^{- 6} A / V^{2}) (\frac{2}{1}) (2.5 V - 0.6 V)} τ_{P H L} = 1.57 n s$

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