Using logic gates, design a 4-output active-low decoder that includes an enable input. Additionally, using flip- flops, design a MOD8 down counter. Connect: The most significant bit (MSB) of the counter output to the least significant bit (LSB) of the decoder input. The intermediate bit of the counter output to the most significant bit (MSB) of the decoder input. The least significant bit (LSB) of the counter output to the decoder enabler. Plot the output variable O3 of the decoder for 16 clock cycles (assumes the counter starts at zero).

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