Homework Help is Here – Start Your Trial Now!
Engineering
Computer Engineering
Use five-stage pipeline containing Fetch, Decode, Memory read, Execute, Write-back units, show the execution of above instructions Data dependencies and control hazards, if detected must be resolved by delaying the pipeline as required. Use the following format: Instructions /Time-step 12 3 4 5 ... LOAD R1, M1 XOR R2, R1, R1 BNEZ R2, Target1 ADD R7, R1, R5 XOR R2, R7, R7 Target1: BEZ R2, Target2 LOAD R3, M2 LOAD R4, M3 ADD R10, R3, R4 Target2: ADD R10, R3, R4 STORE M4, R10 END

Use five-stage pipeline containing Fetch, Decode, Memory read, Execute, Write-back units, show the execution of above instructions Data dependencies and control hazards, if detected must be resolved by delaying the pipeline as required. Use the following format: Instructions /Time-step 12 3 4 5 ... LOAD R1, M1 XOR R2, R1, R1 BNEZ R2, Target1 ADD R7, R1, R5 XOR R2, R7, R7 Target1: BEZ R2, Target2 LOAD R3, M2 LOAD R4, M3 ADD R10, R3, R4 Target2: ADD R10, R3, R4 STORE M4, R10 END

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
See similar textbooks
icon
Related questions
Question
Use five-stage pipeline containing Fetch, Decode, Memory read, Execute, Write-back units, show the execution of above instructions. Data dependencies and control hazards, if detected must be resolved by delaying the pipeline as required. Use the following format: Instructions /Time-step 123 4 5 LOAD R1, M1 XOR R2, R1, R1 BNEZ R2, Target1 ADD R7, R1, R5 XOR R2, R7, R7 Targetl: BEZ R2, Target2 LOAD R3, M2 LOAD R4, M3 ADD R10, R3, R4 Target2: ADD R10, R3, R4 STORE M4, R10 END Calculate the execution time. Assume that a multi-port RAM is used with the CPU running at 3GHZ and each section requires 2 clock cycles.
Transcribed Image Text:Use five-stage pipeline containing Fetch, Decode, Memory read, Execute, Write-back units, show the execution of above instructions. Data dependencies and control hazards, if detected must be resolved by delaying the pipeline as required. Use the following format: Instructions /Time-step 123 4 5 LOAD R1, M1 XOR R2, R1, R1 BNEZ R2, Target1 ADD R7, R1, R5 XOR R2, R7, R7 Targetl: BEZ R2, Target2 LOAD R3, M2 LOAD R4, M3 ADD R10, R3, R4 Target2: ADD R10, R3, R4 STORE M4, R10 END Calculate the execution time. Assume that a multi-port RAM is used with the CPU running at 3GHZ and each section requires 2 clock cycles.
Consider the following assembly code: Instruction Description LOAD R1, M1 Read data from memory address M1 and store in R1. XOR R2, R1, R1 Logical Ex-OR between contents of R1 with R1 and store result in R2 BNEZ R2, Target1 Jump to Target if R2 is non-Zero ADD R7, R1, R5 Add contents of R1 and R5 and store to R7 AND R2, R7, R7 Logical Ex-OR between contents of R7 with R7 and store result in R2 Targetl: BEZ R2, Target2 Jump to Target if R2 is Zero LOAD R3, M2 LOAD R4, M3 ADD R10, R3, R4 Target2: ADD R10, R3, R4 STORE M4, R10 Save contents of R10 to memory address M4 END
Transcribed Image Text:Consider the following assembly code: Instruction Description LOAD R1, M1 Read data from memory address M1 and store in R1. XOR R2, R1, R1 Logical Ex-OR between contents of R1 with R1 and store result in R2 BNEZ R2, Target1 Jump to Target if R2 is non-Zero ADD R7, R1, R5 Add contents of R1 and R5 and store to R7 AND R2, R7, R7 Logical Ex-OR between contents of R7 with R7 and store result in R2 Targetl: BEZ R2, Target2 Jump to Target if R2 is Zero LOAD R3, M2 LOAD R4, M3 ADD R10, R3, R4 Target2: ADD R10, R3, R4 STORE M4, R10 Save contents of R10 to memory address M4 END
Expert Solution
steps

Step by step

Solved in 3 steps with 2 images

SEE SOLUTIONCheck out a sample Q&A here
Blurred answer
Recommended textbooks for you
Computer Networking: A Top-Down Approach (7th Edi…
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Concepts of Database Management
Concepts of Database Management
Computer Engineering
ISBN:
9781337093422
Author:
Joy L. Starks, Philip J. Pratt, Mary Z. Last
Publisher:
Cengage Learning
Prelude to Programming
Prelude to Programming
Computer Engineering
ISBN:
9780133750423
Author:
VENIT, Stewart
Publisher:
Pearson Education
Sc Business Data Communications and Networking, T…
Sc Business Data Communications and Networking, T…
Computer Engineering
ISBN:
9781119368830
Author:
FITZGERALD
Publisher:
WILEY
SEE MORE TEXTBOOKS