This problem tests your ability to predict the cache behavior of C code. You are given the following code to analyze:1 int x[2][128]; 2 int i;3 int sum = 0;45 for (i = 0; i < 128; i++) {6 sum += x[0][i] * x[1][i];7 }Assume we execute this under the following conditions:sizeof(int) = 4.Array x begins at memory address 0x0 and is stored in row-majororder.In each case below, the cache is initially empty.The only memory accesses are to the entries of the array x . Allother variables are stored in registers.Given these assumptions, estimate the miss rates for the followingcases:A. Case 1: Assume the cache is 512 bytes, direct-mapped, with16-byte cache blocks. What is the miss rate?B. Case 2: What is the miss rate if we double the cache size to1,024 bytes?C. Case 3: Now assume the cache is 512 bytes, two-way setassociative using an LRU replacement policy, with 16-bytecache blocks. What is the cache miss rate? D. For case 3, will a larger cache size help to reduce the missrate? Why or why not?E. For case 3, will a larger block size help to reduce the miss rate?Why or why not?
This problem tests your ability to predict the cache behavior of C code.
You are given the following code to analyze:
1 int x[2][128];
2 int i;
3 int sum = 0;
4
5 for (i = 0; i < 128; i++) {
6 sum += x[0][i] * x[1][i];
7 }
Assume we execute this under the following conditions:
sizeof(int) = 4.
Array x begins at memory address 0x0 and is stored in row-major
order.
In each case below, the cache is initially empty.
The only memory accesses are to the entries of the array x . All
other variables are stored in registers.
Given these assumptions, estimate the miss rates for the following
cases:
A. Case 1: Assume the cache is 512 bytes, direct-mapped, with
16-byte cache blocks. What is the miss rate?
B. Case 2: What is the miss rate if we double the cache size to
1,024 bytes?
C. Case 3: Now assume the cache is 512 bytes, two-way set
associative using an LRU replacement policy, with 16-byte
cache blocks. What is the cache miss rate?
D. For case 3, will a larger cache size help to reduce the miss
rate? Why or why not?
E. For case 3, will a larger block size help to reduce the miss rate?
Why or why not?
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