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Logic Equation Y: The truth table A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Input B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 C D 0 0 0 1 1 Workshop 03 Combinational Digital Circuit Design Y = f(A, B, C, D) = m(1,2,3,5,6,7,9,11,13) 0 1 1 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 1 The standard SOP: 0 1 Output Y Product Term (minterm) Sum Term (Maxterm)

Logic Equation Y: The truth table A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Input B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 C D 0 0 0 1 1 Workshop 03 Combinational Digital Circuit Design Y = f(A, B, C, D) = m(1,2,3,5,6,7,9,11,13) 0 1 1 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 1 The standard SOP: 0 1 Output Y Product Term (minterm) Sum Term (Maxterm)

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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Logic Equation Y: The truth table A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Input B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 с 0 Workshop 03 Combinational Digital Circuit Design Y = f(A, B, C, D) = m(1,2,3,5,6,7,9,11,13) 0 1 1 0 0 1 1 0 0 0 1 1 0 1 1 D 0 1 0 The standard SOP: 1 1 0 0 0 1 0 1 1 0 1 0 1 Output Y Product Term (minterm) Sum Term (Maxterm)
Transcribed Image Text:Logic Equation Y: The truth table A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Input B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 с 0 Workshop 03 Combinational Digital Circuit Design Y = f(A, B, C, D) = m(1,2,3,5,6,7,9,11,13) 0 1 1 0 0 1 1 0 0 0 1 1 0 1 1 D 0 1 0 The standard SOP: 1 1 0 0 0 1 0 1 1 0 1 0 1 Output Y Product Term (minterm) Sum Term (Maxterm)
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The minimum SOP: (using Karnaugh's Map)
Transcribed Image Text:The minimum SOP: (using Karnaugh's Map)
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The logic circuit: (From minimum SOP) Number of gates used in the circuit: 2-Input AND gate.. 2-Input OR gate. NOT gate Number of idle gates in the chip: 2-Input AND gate 2-Input OR gate... NOT gute The logic circuit: (From minimum POS) gates gates gates gates gutes Number of gates used in the circuit: 2-Input AND gate 2-Input OR gate... NOT gate Number of idle gates in the chip: 2-Input AND gate... 2-Input OR gate, NOT gate, IC name: IC name: IC name: gates IC name: gates IC name: gates IC name: gates gates gates
Transcribed Image Text:The logic circuit: (From minimum SOP) Number of gates used in the circuit: 2-Input AND gate.. 2-Input OR gate. NOT gate Number of idle gates in the chip: 2-Input AND gate 2-Input OR gate... NOT gute The logic circuit: (From minimum POS) gates gates gates gates gutes Number of gates used in the circuit: 2-Input AND gate 2-Input OR gate... NOT gate Number of idle gates in the chip: 2-Input AND gate... 2-Input OR gate, NOT gate, IC name: IC name: IC name: gates IC name: gates IC name: gates IC name: gates gates gates
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Follow-up Question
The minimum POS: (using Karnaugh's Map)
Transcribed Image Text:The minimum POS: (using Karnaugh's Map)
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The standard POS: The minimum SOP: (using Boolean Algebra)
Transcribed Image Text:The standard POS: The minimum SOP: (using Boolean Algebra)
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