The figure below shows a digital circuit with three inputs (A, B, C) and three outputs (X2, X1, X0). The circuit is composed of the following components: . 74LS138: 3-to-8 line decoder. 74LS151: 8-to-1 multiplexer. 74LS20: Dual 4-input NAND gate. 74LS08: Quad 2-input AND gate. 74LS04: Hex inverter. A U1 YD ۲۱ 1 U2 A c 12 B Y3 хо Y4 Ε Y5 T4L520 12 YB YT с U3 741513 U6:A 300 X1 32 X4 35 11 хт C E 745151 U4 A 74L504 U6:B 74L515 US:A 741503 74L504 X1 U7:A x2 745532 a) Create the truth table for all possible combinations of inputs (A, B, C) and their corresponding outputs (X2, X1, X0). C X2 X1 X0 A B 0 0 0 0 1 1 010 1 101100 0 1 1 1 0 1 1 1 b) Implement the circuit in Verilog using any modeling technique of your choice. Ensure that your implementation considers the propagation delays (as mentioned in the table below) specified in the datasheets of each component [Set time scale to 1ns/1ps]. Verilog Code
The figure below shows a digital circuit with three inputs (A, B, C) and three outputs (X2, X1, X0). The circuit is composed of the following components: . 74LS138: 3-to-8 line decoder. 74LS151: 8-to-1 multiplexer. 74LS20: Dual 4-input NAND gate. 74LS08: Quad 2-input AND gate. 74LS04: Hex inverter. A U1 YD ۲۱ 1 U2 A c 12 B Y3 хо Y4 Ε Y5 T4L520 12 YB YT с U3 741513 U6:A 300 X1 32 X4 35 11 хт C E 745151 U4 A 74L504 U6:B 74L515 US:A 741503 74L504 X1 U7:A x2 745532 a) Create the truth table for all possible combinations of inputs (A, B, C) and their corresponding outputs (X2, X1, X0). C X2 X1 X0 A B 0 0 0 0 1 1 010 1 101100 0 1 1 1 0 1 1 1 b) Implement the circuit in Verilog using any modeling technique of your choice. Ensure that your implementation considers the propagation delays (as mentioned in the table below) specified in the datasheets of each component [Set time scale to 1ns/1ps]. Verilog Code
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Transcribed Image Text:The figure below shows a digital circuit with three inputs (A, B, C) and three outputs (X2, X1, X0).
The circuit is composed of the following components:
.
74LS138: 3-to-8 line decoder.
74LS151: 8-to-1 multiplexer.
74LS20: Dual 4-input NAND gate.
74LS08: Quad 2-input AND gate.
74LS04: Hex inverter.
A
U1
YD
۲۱
1 U2 A
c
12
B
Y3
хо
Y4
Ε
Y5
T4L520
12
YB
YT
с
U3
741513
U6:A
300
X1
32
X4
35
11
хт
C
E
745151
U4 A
74L504
U6:B
74L515
US:A
741503
74L504
X1
U7:A
x2
745532
![a) Create the truth table for all possible combinations of inputs (A, B, C) and their
corresponding outputs (X2, X1, X0).
C X2 X1 X0
A B
0
0
0
0
1
1
010
1
101100
0
1
1
1
0
1 1
1
b) Implement the circuit in Verilog using any modeling technique of your choice. Ensure
that your implementation considers the propagation delays (as mentioned in the table
below) specified in the datasheets of each component [Set time scale to 1ns/1ps].
Verilog Code](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Ff0c7c0e9-1042-4b47-9e78-c6aaeaae6479%2F77118d4f-c723-46a2-85df-0fae4b203908%2Fknfagmw_processed.png&w=3840&q=75)
Transcribed Image Text:a) Create the truth table for all possible combinations of inputs (A, B, C) and their
corresponding outputs (X2, X1, X0).
C X2 X1 X0
A B
0
0
0
0
1
1
010
1
101100
0
1
1
1
0
1 1
1
b) Implement the circuit in Verilog using any modeling technique of your choice. Ensure
that your implementation considers the propagation delays (as mentioned in the table
below) specified in the datasheets of each component [Set time scale to 1ns/1ps].
Verilog Code
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