The following circuit shows the carry-lookahead adder design. Assuming the delay for each gate is 2.2 ns, and there is no fan-in issue (meaning a gate can take as many inputs as possible). Consider a n-bit carry-lookahead adder, what is the duration (in ns) you have to wait until the correct C is generated? Carry-Lookahead Adder Ci+1=g; +pi ci = 8; + Pi (8-1 + Pi-1 C1.1) g+Pi8-1 + PiPi-11-1 = 81+Pi81-1+ Pi Pi-181-2+...+P1 Poco g₁ = xi yi Pi = x; + yi 2.2*(3+7*2) 2.2*3 2.2*8*n 2.2 n "

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