The following circuit shows a 3-bit ripple counter consisting of three positive edge triggered D flip-flops and a negation gate on the clock input C. 100 Q D Q Q Q. Q, a) Complete the following timing diagram. Assume that gate delays are very short compared to the speed of the clock signal (i.e., you can ignore the impact of gate delays). C Qo Qo Q1 Q1 Q2 Q2 10 12 b) Can you make ripple counters arbitrary “long" or is there a limit on the number of D flip flops that can be chained? Explain. || || ||

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